Method and apparatus on (110) surfaces of silicon structures with conduction in the <110> direction

• US 6,960,821 B2
• Filed: 06/17/2003
• Issued: 11/01/2005
• Est. Priority Date: 08/31/1999
• Status: Expired due to Fees

• Current Assignee: Recaro Aircraft Seating GmbH & Company
• Original Assignee: Micron Technology, Inc.
• Inventors: Forbes, Leonard, Noble, Wendell P., Reinberg, Alan R.
• Primary Examiner(s): Tran, Minhloan
• Assistant Examiner(s): Dickey, Thomas L
• Application Number:
  US10/463,261
• Publication Number:
  US 20030209782A1
• Time in Patent Office: 868 Days
• Field of Search: 257206-208, 257/210, 257/288, 257/296, 257/341, 257/343, 257/396, 257/397, 257/521, 257/527, 257/627, 257/628
• US Class Current: 257/628
• CPC Class Codes: H01L 21/2255 the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/66787 with a gate at the side of the channel
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/056 the transistor being a FinFET
• CPC Class Codes: Y10S 438/973 Substrate orientation

Abstract

Improved methods and structures are provided that are lateral to surfaces with a (110) crystal plane orientation such that an electrical current of such structures is conducted in the <110> direction. Advantageously, improvements in hole carrier mobility of approximately 50% can be obtained by orienting the structure'"'"'s channel in a (110) plane such that the electrical current flow is in the <110> direction. Moreover, these improved methods and structures can be used in conjunction with existing fabrication and processing techniques with minimal or no added complexity.

Claims

1. A semiconductor device, comprising:

an array of lateral transistors formed on a trench wall of a trench in a silicon wafer, wherein the silicon wafer has a top surface in a (100) crystal plane orientation an the trench wall has a (110) crystal plane orientation, and wherein each lateral transistor includes;

a first conductive region in a first portion of the trench wall;

a second conductive region in a second portion of the trench wall; and

a third conductive region in a third portion of the trench wall, such that the third conductive region is between the first and second conductive regions and wherein each lateral transistor is configured to conduct an electrical current between the first conductive regions and the second conductive region in a <

110>

direction; and

a wordline coupled to a gate of each lateral transistor formed on the trench wall of the trench of the silicon wafer.

2. The semiconductor device of claim 1, wherein the silicon wafer includes a Silicon On Insulator (SOI) material.

3. The semiconductor device of claim 1, wherein each lateral transistor configured to conduct the electrical current in the <

110>

direction includes each lateral transistor being configured to conduct an electrical current parallel to a top surface of the silicon wafer.

4. The semiconductor device of claim 1, wherein the third conductive region in each lateral transistor includes a channel region.

5. An electronic system comprising:

a processor;

a memory coupled to the processor, wherein the memory further includes;

an array of lateral transistors formed on a trench wall of a trench in a silicon wafer, wherein the silicon wafer has a top surface with a (100) crystal plane orientation and the trench wall has a (110) crystal plane orientation; and

wherein each lateral transistor in the array of lateral transistors includes;

a first conductive region in a first portion of the trench, such that the first conductive region is lateral to the trench wall;

a second conductive region in a second portion of the trench such that the second conductive region is lateral to the trench wall; and

a third conductive region in a third portion of the trench, such that the third conductive region is lateral to the trench wall and between the first and second conductive regions and wherein an electrical current is capable of flowing between the first conductive region and the second conductive region in a <

110>

direction.

6. The electronic system of claim 5, wherein the memory includes a dynamic random access memory.

7. The electronic system of claim 5, wherein the silicon wafer includes a Silicon On Insulator (SOI) material.

8. The electronic system of claim 5, wherein each lateral transistor includes a gate which opposes the third conductive region.

9. The electronic system of claim 5, wherein each lateral transistor includes a gate oxide separating the gate and the third conductive region.

10. The electronic system of claim 8, further including a wordline coupling together the gates of the lateral transistors.

11. A semiconductor device, comprising:

an array of memory elements, each memory element comprising;

a first conductive region of a first type formed laterally to a trench wall having a (110) crystal plane orientation;

a second conductive region of the first type formed laterally to the trench wall; and

a third conductive region of a second type disposed laterally to the trench wall and separating the first and second conductive regions to permit electrical current to be conducted in a <

110>

direction between the first and second conductive regions.

12. A semiconductor device, comprising:

an array of memory elements, each memory element comprising;

a layer of conductive material of a first type formed on a substrate;

at least one trench formed in the layer of conductive material and including a trench wall substantially perpendicular to a top surface of the substrate and including a (110) crystal plane orientation;

a first conductive region of a second type formed in a plane of the trench wall;

a second conductive region of the second type formed in the plane of the trench wall; and

a third conductive region of the layer of conductive material disposed in the plane of the trench wall and separating the first and second conductive regions to permit electrical current to be conducted in a <

110>

direction.

13. A semiconductor device, comprising:

a layer of conductive material of a first type formed on a substrate;

at least one trench formed in the layer of conductive material, the at least one trench including a trench wall substantially perpendicular to a top surface of the substrate and including a (110) crystal plane orientation;

at least one memory element formed laterally to the at least one trench wall, the at least one memory element comprising;

a first conductive region of a second type formed laterally to the trench wall;

a second conductive region of the second type formed laterally to the trench wall; and

a third conductive region of the layer of conductive material disposed laterally to the trench wall and separating the first and second conductive regions to permit electrical current to be conducted in a >

110>

direction.