Low voltage differential signal driver circuit and method

• US 6,960,931 B2
• Filed: 10/30/2002
• Issued: 11/01/2005
• Est. Priority Date: 10/30/2002
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Turcotte, Marc
• Primary Examiner(s): Tran, Anh Q.
• Application Number:
  US10/283,721
• Publication Number:
  US 20050073338A1
• Time in Patent Office: 1,098 Days
• Field of Search: 326 30- 34, 326/87
• US Class Current: 326/30
• CPC Class Codes: H03K 17/164 using parallel switching arrangements
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/0286 Provision of wave shaping within the driver wave shaping per se H04L25/03834

Abstract

A low voltage differential signal driver that generates a differential signal using a switching sequencer for ensuring uniform transitions of the output signals, and a driver that includes a network of matched resistors for generating the output signals. The network of matched resistors can be configured based on one or more sequencing signals generated by the switching sequencer.

Claims

1. A differential signal driver comprising:

a switching sequencer capable of providing a plurality of sequencing signals; and

a driver having a control and an output stage, the control stage generating a plurality of control signals for each one of the sequencing signals, the output stage generating a first output signal and a second output signal in response to receiving the plurality of control signals.

4. The differential signal driver of claim 1, wherein the plurality of sequencing signals are provided at substantially uniform propagation delays.

5. The differential signal driver of claim 1, wherein the plurality of control signals are generated using functionally balanced circuits.

2. A circuit for generating a differential voltage signal comprising:

first and second resistor networks each having a plurality of resistor sets capable of generating a voltage level at a different output in response to a plurality of sequencing signals, each one of the resistor sets including;

a first resistor having a first enable state, and being gated by a first gate; and

a second resistor having a second enable state that is complementary to the first enable state during normal operation, and being gated by a second gate.

6. The circuit of claim 2, wherein each resistor set further comprises a third resistor that provides parallel impedance to both the first resistor and the second resistor.

7. The circuit of claim 6, wherein the third resistor is gated by a third gate, and wherein the first gate, the second gate, and the third gate are tristated using an enable signal.

8. The circuit of claim 2, wherein each resistor set on the first network is associated with a unique resistor set on the second network.

9. The circuit of claim 8, wherein each associated pair of resistor sets are configured based on one of the sequencing signals.

10. The circuit of claim 2, further comprising:

a switching sequencer for providing the plurality of sequencing signals based on a digital input, wherein the plurality of sequencing signals are provided at uniform propagation delays; and

a control stage for generating a set of control signals for each of the plurality of sequencing signals.

11. The differential signal driver of claim 10, wherein the switching sequencer includes a plurality of inverters, and wherein each sequencing signal is an output of an inverter.

3. A method of generating a differential voltage signal, the method comprising:

receiving a digital input;

providing a plurality of sequencing signals based on the digital input;

generating a set of control signals for each of the plurality of sequencing signals;

gating a pair of resistors on a first resistor network and a pair of resistors on a second resistor network using one of the sets of control signals;

generating a first voltage at a first output based on the first resistor network; and

generating a second voltage at a second output based on the second resistor network, wherein a difference of the first voltage and the second voltage comprises the differential voltage signal.

12. The method of claim 3, wherein the gating step includes, for each pair of resistors:

disabling an electrical path for a first resistor on the first resistor network based on a first control signal;

enabling an electrical path for a second resistor on the first resistor network based on a second control signal;

disabling an electrical path for a first resistor on the second resistor network based on a third control signal; and

enabling an electrical path for a second resistor on the second resistor network based on a fourth control signal.

13. The method of claim 12, wherein the first control signal is complementary to the fourth control signal and the second control signal is complementary to the third control signal.

14. The method of claim 3, wherein the generating a set of driver signals steps includes:

receiving an enable signal;

receiving a sequencing signal;

generating a first pair of control signals based on a logical NAND operation performed on the enable signal and the sequencing signal; and

generating a second pair of control signals based on a logical NOR operation performed on a complement of the enable signal and the sequencing signal.

15. The method of claim 3, wherein the configuring step further includes:

gating a third resistor on the first resistor network in parallel with each of the pair of resistors on the first resistor network;

gating a third resistor on the second resistor network in parallel with each of the pair of resistors on the second resistor network; and

tristating each resistor on each resistor network using an enable signal.