Synchronous content addressable memory

• US 6,961,810 B2
• Filed: 12/22/2003
• Issued: 11/01/2005
• Est. Priority Date: 10/30/1997
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Netlogic Microsystems Incorporated (Broadcom, Inc.)
• Inventors: Nataraj, Bindiganavale S., Khanna, Sandeep, Srinivasan, Varadarajan
• Primary Examiner(s): PEIKARI, BEHZAD
• Application Number:
  US10/743,962
• Publication Number:
  US 20040139276A1
• Time in Patent Office: 680 Days
• Field of Search: 365/49, 365/226, 380/5, 380/9, 711/108
• US Class Current: 711/108
• CPC Class Codes: G11C 15/00 Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
• CPC Class Codes: G11C 15/04 using semiconductor elements

Abstract

A CAM device to perform in one clock cycle: (1) receive comparand data from a comparand bus; (2) receive an instruction; (3) perform the comparison of the comparand data with a first group of CAM cells; (4) generate a match address for a location in the CAM array that stores data matching the comparand data; (5) access data stored in a second group of the CAM cells in the CAM array, wherein the second group of CAM cells may store data associated with the matched location; and (6) output to an output bus the match address, the data stored in the second group of CAM cells, and/or status information corresponding to the matched address or the second group of CAM cells.

Claims

1. A method of reading data from a synchronous content addressable memory (CAM) device, comprising the steps of:

instructing the CAM device to compare comparand data with data stored in a plurality of first CAM cells;

comparing the comparand data with the data stored in each of the plurality of first CAM cells;

sensing data stored in a second CAM cell; and

outputting the sensed data from the CAM device, wherein the instructing, comparing, sensing, and outputting steps all occur in one clock cycle.

2. The method of claim 1 wherein comparing the comparand data with the data stored in each of the plurality of first CAM cells comprises providing the comparand data to the plurality of first CAM cells via a plurality of compare lines.

3. The method of claim 2 wherein sensing data stored in a second CAM cell comprises receiving data in a sense amplifier coupled to the second CAM cell via at least one bit line.

4. The method of claim 3 wherein the CAM device comprises an array of CAM cells that includes the plurality of first CAM cells and the second CAM cell.

5. The method of claim 3 wherein the plurality of first CAM cells includes the second CAM cell.

6. The method of claim 1 wherein sensing data stored in the second CAM cell comprises addressing a row of CAM cells that includes the second CAM cell.

7. The method of claim 6 wherein addressing a row of CAM cells that includes the second CAM cell comprises addressing a row of CAM cells indicated by a match address generated in a prior compare operation within the CAM device.

8. The method of claim 1 wherein addressing the row of CAM cells indicated by a match address generated in a prior compare operation within the CAM device comprises:

generating the match address within a priority encoder of the CAM device;

providing the match address from the priority encoder to an address decoder of the CAM device; and

decoding the match address within the address decoder to activate a word line coupled to the row of CAM cells.

9. The method of claim 8 wherein providing the match address from the priority encoder to the address decoder comprises latching the match address in an address latch and outputting the match address from the address latch to the address decoder.

10. The method of claim 8 wherein providing the match address from the priority encoder to the address decoder comprises outputting the match address from the priority encoder to an address selector and configuring the address selector to pass the match address to the address decoder.

11. The method of claim 10 wherein configuring the address selector to pass the match address to the address decoder comprises asserting a control signal to the address selector in response to an instruction received from an external device.

12. A synchronous content addressable memory (CAM) device comprising:

an array of CAM cells;

circuitry to compare first comparand data with contents of the array of CAM cells during a first clock cycle;

circuitry to sense data stored in a selected row of CAM cells within the array of CAM cells during the first clock cycle; and

circuitry to output the sensed data from the CAM device during the first clock cycle.

13. The synchronous CAM device of claim 12 wherein the circuitry to compare first comparand data with contents of the array of CAM cells comprises an instruction decoder to receive an instruction to compare the first comparand data with the contents of the array of CAM cells.

14. The synchronous CAM device of claim 12 wherein the array of CAM cells comprises a plurality of columns of CAM cells, and wherein the circuitry to compare first comparand data with contents of the array of CAM cells comprises a plurality of compare lines coupled to a plurality of columns of CAM cells, and wherein the circuitry to sense data stored in the selected row of CAM cells comprises a plurality of bit lines coupled to the plurality of columns of CAM cells.

15. The synchronous CAM device of claim 12 further comprising match circuitry, including a priority encoder, to generate a match address based upon a comparison of second comparand data with contents of the array of CAM cells.

16. The synchronous CAM device of claim 15 wherein the circuitry to sense data stored in a selected row of CAM cells comprises address decoding circuitry coupled to receive the match address from the match circuitry and configured to decode the match address to enable access to the selected row of CAM cells.

17. The synchronous CAM device of claim 16 wherein the address decoding circuitry comprises an address selector to select the match address from among a plurality of address sources.

18. A synchronous content addressable memory (CAM) device comprising:

an array of CAM cells;

means for comparing first comparand data with contents of the array of CAM cells during a first clock cycle;

means for sensing data stored in a selected row of CAM cells within the array of CAM cells during the first clock cycle; and

means for outputting the sensed data from the CAM device during the first clock cycle.

19. The synchronous CAM device of claim 18 further comprising means for generating a match address based upon a comparison of second comparand data with contents of the array of CAM cells, and wherein the means for sensing data stored in the selected row of CAM cells comprises means for decoding the match address to enable access to the selected row of CAM cells.