Data carrier comprising memory means for storing information significant for intermediate operating states

• US 6,961,829 B2
• Filed: 06/04/2002
• Issued: 11/01/2005
• Est. Priority Date: 06/06/2001
• Status: Active Grant

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: Preishuber-Pfluegl, Josef
• Primary Examiner(s): Peugh, Brian R.
• Application Number:
  US10/161,751
• Publication Number:
  US 20020186789A1
• Time in Patent Office: 1,246 Days
• Field of Search: 711/154, 711/150, 711/151, 711/156, 711/163, 340/572.3, 340/10.2, 340/10.1, 340/10.3, 235/375, 235/436, 375/316
• US Class Current: 711/154
• CPC Class Codes: G06K 19/0723 the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs
• CPC Class Codes: G06K 7/10861 sensing of data fields affixed to objects or articles, e.g. coded labels postal sorting B07C3/14, conveying articles B65G47/48

Abstract

A data carrier (2) or an integrated circuit (41) for a data carrier (2) comprises a memory (54) which is designed to store intermediate operating state information (ZS, CI16, CI20, BRS) significant for an intermediate operating state of the data carrier (2) or the integrated circuit (41) and comprises a memory control device (51), which after the occurrence of information significant for intermediate operating states ensures that this intermediate operating state information is stored in the memory (54) and comprises a control device (51), which—after the detection of the non-existence of the supply voltage (V) required for faultless operation during execution of a communication sequence interrupted by this non-existence and the subsequent detection of the re-existence of the supply voltage (V)—ensure that the data carrier (2) or the integrated circuit (41) is controlled in an intermediate operating state for which intermediate operating state information (ZS, CI16, CI20, BRS) stored in the memory (54) is significant.

Claims

1. A data carrier (2) comprising communication means (50) for communication with at least one communication station (1) in accordance with a communication sequence executed during the communication, the communication sequence comprising several communication steps, and in the data carrier (2) an intermediate operating state occurs as a result of a communication step of specific communication steps, and in the data carrier (2) intermediate operating state information significant for an intermediate operating state of specific intermediate operating states (ZS, CI16, CI20, BRS) occurs, and the data carrier (2) comprising detection means (46) to detect the existence of at least one operating variable (V) required for the operation of the data carrier (2), and the data carrier (2) comprising memory means (54) for storing information, the memory means (54) being designed for storing the intermediate operating state information (ZS, CI16, CI20, BRS) significant for an intermediate operating state, and the data carrier (2) comprising memory control means (51) which are designed so that after the occurrence of an intermediate operating state information (ZS, CI16, CI20, BRS) significant for an intermediate operating state they ensure that this intermediate operating state information (ZS, CI16, CI20, BRS) significant for an intermediate operating state is stored in the memory means (54), and the data carrier (2) comprising control means (51), which are designed so that—

after the detection of the non-existence of the at least one operating variable (V) during the interrupted execution of the communication sequence due to this non-existence of the at least one operating variable (V) and the subsequent detection of the re-existence of the at least one operating variable (V) by the detection means (46)—

they ensure that the data carrier (2) is controlled in an intermediate operating state for which intermediate operating state an intermediate operating state information (ZS, CI16, CI20, BRS) stored in the memory means (54) is significant.

2. A data carrier (2) as claimed in claim 1 wherein the detection means (46) are designed for detecting the existence of a sufficiently high supply voltage (V) for the operation of the data carrier (2).

3. A data carrier (2) as claimed in claim 1 wherein the control means (51) are designed so that the data carrier (2) is controlled in this intermediate operating state for which intermediate operating state the significant intermediate operating state information (ZS, CI16, CI20, BRS) was stored as the last intermediate operating state information (ZS, CI16, CI20, BRS) in the memory means (54) before the detection of the non-existence of the at least one operating variable (V).

4. A data carrier (2) as claimed in claim 1 wherein the control means (51) are designed so that the data carrier (2) is controlled in at least one intermediate operating state occurring during the course of the execution of an anticollision procedure.

5. A data carrier (2) as claimed in claim 1 wherein the control means (51) are designed so that the data carrier (2) is controlled in an intermediate operating state occurring as a result of the execution of a password procedure.

6. A data carrier (2) as claimed in claim 1 wherein the memory means (54) being formed by a FRAM.

7. A data carrier (2) as claimed in claim 1 wherein the memory means (54) comprising at least two memory stages (90, 91, 92) each comprising a capacitive cell (93, 94, 95), and the two memory stages (P0, P1, P2) are suitable for the time-limited storage of the intermediate operating state information significant for an intermediate operating state.

8. A data carrier (2) as claimed in claim 1 comprising erasing means (71) by which erasing means (71) the memory means (54) can be erased in order to be able to delete the respective intermediate operating state information (ZS, CI16, CI20, BRS) significant for an intermediate operating state and stored in the memory means (54).

9. An integrated circuit (41) for a data carrier (2) comprising communication means (50) for communication with at least one communication station (1) in accordance with a communication sequence executed during the communication, the communication sequence comprising several communication steps, and in the integrated circuit (41) an intermediate operating state occurs as a result of a communication step of certain communication steps, and in the integrated circuit (41) intermediate operating state information significant for an intermediate operating step of specific intermediate operating states (ZS, CI16, CI20, BRS) occurs, and the integrated circuit (41) comprising detection means (46) to detect the existence of at least one operating variable (V) required for the operation of the integrated circuit (41), the integrated circuit (41), and the integrated circuit (41) comprising memory means (54) for storing information, the memory means (54) being designed for storing the intermediate operating state information (ZS, CI16, CI20, BRS) significant for an intermediate operating state, and the integrated circuit (41) comprising memory control means (51) which are designed so that after the occurrence of an intermediate operating state information (ZS, CI16, CI20, BRS) significant for an intermediate operating state they ensure that this intermediate operating state information (ZS, CI16, CI20, BRS) significant for an intermediate operating state is stored in the memory means (54), and the integrated circuit (41) comprising control means (51), which are designed so that—

after the detection of the non-existence of the at least one operating variable (V) during the interrupted execution of the communication sequence due to this non-existence of the at least one operating variable (V) and the subsequent detection of the re-existence of the at least one operating variable (V) by the detection means (46)—

they ensure that the integrated circuit (41) is controlled in an intermediate operating state for which intermediate operating state an intermediate operating state information (ZS, CI16, CI20, BRS) stored in the memory means is significant.

10. An integrated circuit (41) as claimed in claim 9 wherein the detection means (46) are designed so for detecting the existence of a sufficiently high supply voltage (V) for the operation of the integrated circuit (41).

11. An integrated (41) circuit as claimed in claim 9 wherein the control means (51) are designed so that the integrated circuit (41) is controlled in this intermediate operating state for which intermediate operating state the significant intermediate operating state information (ZS, CI16, CI20, BRS) was stored as the last intermediate operating state information (ZS, CI16, CI20, BRS) in the memory means (54) before the detection of the non-existence of the at least one operating variable (V).

12. An integrated circuit (41) as claimed in claim 9 wherein the control means (51) are designed so that the integrated circuit (41) is controlled in at least intermediate operating state occurring during the course of the execution of an anticollision procedure.

13. An integrated circuit (41) as claimed in claim 9 wherein the control means (51) are designed so that the integrated circuit (41) is controlled in an intermediate operating state as a result of the execution of a password procedure.

14. An integrated circuit (41) as claimed in claim 9 wherein the memory means (54) being formed by a FRAM.

15. An integrated circuit (41) as claimed in claim 9 wherein the memory means (54) comprising at least two memory stages (90, 91, 92) each comprising a capacitive cell (93, 94, 95), and the two memory stages (P0, P1, P2) are suitable for the time-limited storage of the intermediate operating state information significant for an intermediate operating state.

16. An integrated circuit (41) as claimed in claim 9 comprising erasing means (71) by which erasing means (71) the memory means (54) can be erased to be able to delete the respective intermediate operating state information (ZS, CI16, CI20, BRS) significant for an intermediate operating state and stored in the memory means (54).