Method of making near chip size integrated circuit package

• US 6,962,829 B2
• Filed: 05/17/2002
• Issued: 11/08/2005
• Est. Priority Date: 10/31/1996
• Status: Expired due to Term

• Current Assignee: Amkor Technology Singapore Holding Pte., Ltd. (Amkor Technology Incorporated)
• Original Assignee: Amkor Technology Incorporated
• Inventors: Hollaway, Roy D., Panczak, Anthony E., Glenn, Thomas P.
• Primary Examiner(s): Chambliss, Alonzo
• Application Number:
  US10/150,400
• Publication Number:
  US 20020168798A1
• Time in Patent Office: 1,271 Days
• Field of Search: 438/33, 438/68, 438/113, 438/114, 438/458, 438/459, 438/462, 438/464, 438107-110, 438125-127, 298/32, 298/35, 298/41
• US Class Current: 438/33
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/06135 Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/92247 the second connecting process involving a wire connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/552 : Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01087 : Francium [Fr]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15183 : in a single layer of the multilayer substrate
• CPC Class Codes: H01L 2924/15184 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: Y10T 29/49135 : and shaping, e.g., cutting or bending, etc.

Abstract

A plurality of integrated circuit chip (IC chip) packages are fabricated simultaneously from a single insulating substrate having sections. In each section, an IC chip is attached. Bonding pads on the IC chip are electrically connected to first metallizations on a substrate first surface. The first metallizations, IC chip including bonding pads and first substrate surface are then encapsulated. Interconnection balls or pads are formed at substrate bonding locations on a substrate second surface, the interconnection pads or balls being electrically connected to corresponding first metallizations. The substrate and encapsulant are then cut along the periphery of each section to form the plurality of IC chip packages.

Claims

1. A method of forming a plurality of integrated circuit chip packages, said method comprising:

providing a substrate having a plurality of sections, each of said sections having first metallizations formed on a first surface of said substrate;

coupling an integrated circuit chip to a corresponding one of each of said sections of said substrate;

electrically connecting each said integrated circuit chip to said first metallizations on said corresponding one of said sections;

encapsulating said integrated circuit chips, said first metallizations and said first surface of said substrate with a layer of an encapsulant, wherein said layer of the encapsulant has an outer surface overlying the integrated circuit chips;

placing the outer surface of the layer of the encapsulant on a mounting surface, and immobilizing the encapsulated substrate on said mounting surface;

cutting said encapsulated substrate while on said mounting surface along a periphery of each of said sections to form said plurality of integrated circuit chip packages.

2. The method of claim 1, wherein said mounting surface is a tape with an adhesive layer thereon, wherein the adhesive layer immobilizes the encapsulated substrate, and the layer of the encapsulant comprises a first layer of an electrically insulative encapsulant, and a second layer of an electrically conductive encapsulant at said outer surface.

3. The method of claim 1, further comprising electrically testing said packages while said packages are immobilized on said mounting surface.

4. The method of claim 1, wherein each of said sections has second metallizations formed on a second surface of said substrate opposite said first surface and electrically conductive paths extending through said substrate from said first metallizations to said second metallizations.

5. The method of claim 4, further comprising forming interconnection balls on said second surface of said substrate at each of said sections, each of said interconnection balls being in electrical connection with one of said second metallizations.

6. The method of claim 1, wherein the layer of the encapsulant comprises a first layer of an electrically insulative encapsulant, and a second layer of an electrically conductive encapsulant at said outer surface.

7. The method of claim 1, wherein said mounting surface is a tape with an adhesive layer thereon, wherein the adhesive layer contacts the outer surface of the layer of encapsulant and thereby immobilizes the encapsulated substrate.

8. A method of forming a plurality of integrated circuit chip packages, said method comprising the steps of:

providing a substrate having a first surface and a plurality of sections, each said section having an integrated circuit chip coupled to the first surface of the substrate within the respective section, wherein a layer of an encapsulant covers the first surface of the substrate and the integrated circuit chips, said layer of the encapsulant having an outer surface overlying the integrated circuit chips;

placing the outer surface of the layer of the encapsulant on a mounting surface, and immobilizing the encapsulated substrate thereon;

cutting said encapsulated substrate along a periphery of each of said sections to form said plurality of integrated circuit chip packages.

9. The method of claim 8, wherein said mounting surface is a tape with an adhesive layer thereon, wherein the adhesive layer immobilizes the encapsulated substrate, and the layer of the encapsulant comprises a first layer of an electrically insulative encapsulant, and a second layer of an electrically conductive encapsulant at said outer surface.

10. The method of claim 8, further comprising electrically testing said packages while said packages are immobilized on said mounting surface.

11. The method of claim 10, further comprising forming interconnection balls on a second surface of said substrate at each of said sections, said interconnection balls being electrically coupled to the integrated circuit chip of the respective section.

12. The method of claim 8, wherein the layer of the encapsulant comprises a first layer of an electrically insulative encapsulant, and a second layer of an electrically conductive encapsulant at said outer surface.

13. The method of claim 8, wherein said mounting surface is a tape with an adhesive layer thereon, wherein the adhesive layer contacts the outer surface of the layer of encapsulant and thereby immobilizes the encapsulated substrate.

14. A method of forming a plurality of integrated circuit chip packages, said method comprising the steps of:

providing a substrate having a plurality of sections, each said section having an integrated circuit chip coupled to a first surface of the substrate within the section, wherein a layer of an encapsulant covers the first surface of the substrate and the integrated circuit chips, said layer of the encapsulant having an outer surface overlying the integrated circuit chips;

placing the outer surface of the layer of the encapsulant on a mounting surface, and immobilizing the encapsulated substrate thereon; and

cutting said encapsulated substrate from the substrate through the layer of the encapsulant along a periphery of each of said sections while immobilized on said mounting surface to form said plurality of integrated circuit chip packages.

15. The method of claim 14, wherein said mounting surface is a tape with an adhesive layer thereon, wherein the adhesive layer immobilizes the encapsulated substrate, and the layer of the encapsulant comprises a first layer of an electrically insulative encapsulant, and a second layer of an electrically conductive encapsulant at said outer surface.

16. The method of claim 15, further comprising electrically testing said packages while said packages are immobilized on said mounting surface.

17. The method of claim 16, further comprising forming interconnection balls on a second surface of said substrate at each of said sections, each of said interconnection balls being in electrical connection with the integrated circuit chip of the respective section.

18. The method of claim 14, wherein the layer of the encapsulant comprises a first layer of an electrically insulative encapsulant, and a second layer of an electrically conductive encapsulant at said outer surface.

19. The method of claim 14, wherein said mounting surface is a tape with an adhesive layer thereon, wherein the adhesive layer contacts the outer surface of the layer of encapsulant and thereby immobilizes the encapsulated substrate.