Dual strain-state SiGe layers for microelectronics

• US 6,963,078 B2
• Filed: 03/15/2003
• Issued: 11/08/2005
• Est. Priority Date: 03/15/2003
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: International Business Machines Corporation
• Inventors: Chu, Jack Oon
• Primary Examiner(s): CRANE, SARA W
• Application Number:
  US10/389,145
• Publication Number:
  US 20040178406A1
• Time in Patent Office: 969 Days
• Field of Search: 257/19, 257/190, 257/192
• US Class Current: 257/19
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0245 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02488 Insulating materials
• CPC Class Codes: H01L 21/02502 consisting of two layers
• CPC Class Codes: H01L 21/02505 consisting of more than two layers
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02538 Group 13/15 materials
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/7782 with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET

Abstract

A strained crystalline layer having a tensilely strained SiGe portion and a compressively strained SiGe portion is disclosed. The strained crystalline layer is epitaxially bonded, or grown, on top of a SiGe relaxed buffer layer, in a way that the tensilely strained SiGe has a Ge concentration below that of the SiGe relaxed buffer, and the compressively strained SiGe has a Ge concentration above that of the SiGe relaxed buffer. The strained crystalline layer and the relaxed buffer can reside on top a semi-insulator substrate or on top of an insulating divider layer. In some embodiments the tensile SiGe layer is pure Si, and the compressive SiGe layer is pure Ge. The tensilely strained SiGe layer is suited for hosting electron conduction type devices and the compressively strained SiGe is suited for hosting hole conduction type devices. The strained crystalline layer is capable to seed an epitaxial insulator, or a compound semiconductor layer.

Claims

1. A strained crystalline layer having a tensilely strained SiGe portion and a compressively strained SiGe portion, wherein said tensilely strained SiGe portion and said compressively strained SiGe portion are in coplanar spatial relation, and said compressively strained SiGe having higher Ge concentration than said tensilely strained SiGe, and the Ge concentration in said compressively strained SiGe is above 90%.

2. The strained crystalline layer of claim 1, wherein said tensilely strained SiGe is having up to about 15% Ge concentration.

3. The strained crystalline layer of claim 2, wherein said tensilely strained SiGe is having essentially 0% Ge concentration.

4. The strained crystalline layer of claim 1, wherein said compressively strained SiGe is having essentially 0% Si concentration.

5. The strained crystalline layer of claim 1, wherein said tensilely strained SiGe is having up to about 1% C concentration.

6. The strained crystalline layer of claim 1, wherein said compressively strained SiGe is having up to about 1% C concentration.

7. The strained crystalline layer of claim 1, wherein said compressively strained SiGe is occupying essentially a plurality of island regions.

8. The strained crystalline layer of claim 1, wherein said tensilely strained SiGe is occupying essentially a plurality of island regions.

9. The strained crystalline layer of claim 1, wherein a first crystalline insulating layer is epitaxially bonded on top of said strained crystalline layer, and wherein said first crystalline insulating layer is between about 0.3 nm and 1.5 nm thick.

10. The strained crystalline layer of claim 9 wherein said first crystalline insulating layer is consisting essentially of SiO₂.

11. The strained crystalline layer of claim 9 wherein said first crystalline insulating layer is consisting essentially of silicon oxynitride.

12. The strained crystalline layer of claim 1, further comprising an isolating trench, wherein said isolating trench separates said tensilely strained SiGe portion and said compressively strained SiGe portion.

13. The strained crystalline layer of claim 1, wherein said strained crystalline layer being part of a layered structure, wherein said layered structure comprising:

a substrate;

a SiGe relaxed buffer disposed on top of said substrate; and

said strained crystalline layer epitaxially bonded on top of said SiGe relaxed buffer, wherein said tensilely strained SiGe having Ge concentration below that of said SiGe relaxed buffer, and said compressively strained SiGe having Ge concentration above that of said SiGe relaxed buffer.

14. The strained crystalline layer of claim 1, wherein said strained crystalline layer being part of a layered structure, wherein said layered structure comprising:

a Si substrate;

a support structure epitaxially bonded on top of said Si substrate;

a SiGe relaxed buffer epitaxially bonded on top of said support structure; and

said strained crystalline layer epitaxially bonded on top of said SiGe relaxed buffer, wherein said tensilely strained SiGe having Ge concentration below that of said SiGe relaxed buffer, and said compressively strained SiGe having Ge concentration above that of said SiGe relaxed buffer.

15. The strained crystalline layer of claim 1, wherein said strained crystalline layer being part of a layered structure, wherein said layered structure comprising:

a substrate;

an insulating divider layer disposed on top of said substrate;

a SiGe relaxed buffer disposed on top of said insulating divider layer; and

said strained crystalline layer epitaxially bonded on top of said SiGe relaxed buffer, wherein said tensilely strained SiGe having Ge concentration below that of said SiGe relaxed buffer, and said compressively strained SiGe having Ge concentration above that of said SiGe relaxed buffer.

16. The strained crystalline layer of claim 15, wherein said strained crystalline layer is between about 0.1 nm and 100 nm thick.

17. The strained crystalline layer of claim 16, wherein said strained crystalline layer is between about 0.5 nm and 50 nm thick.

18. The strained crystalline layer of claim 15, wherein said SiGe relaxed buffer Is between about 0.25 nm and 100 nm thick.

19. The strained crystalline layer of claim 18, wherein said SiGe relaxed buffer is between about 5 nm and 60 nm thick.

20. The strained crystalline layer of claim 15, wherein an insulating material in said insulating divider layer is selected from the group consisting of a silicon-oxide, a silicon-nitride, an aluminum-oxide, lithium-niobate, a “

low-k”

material, a “

high-k”

material, end combinations of these materials thereof.

21. The strained crystalline, layer of claim 20, wherein said insulating divider layer comprises a between about 0.3 nm and 1.5 nm thick second crystalline SiO₂ layer, wherein said second crystalline SiO₂ layer is epitaxially bonded to said SiGe relaxed buffer layer.

22. The strained crystalline layer of claim 15, wherein said tensilely strained SiGe is hosting at least one electron conduction type device and wherein said compressively strained SiGe is hosting at least one hole conduction type device.

23. The strained crystalline layer of claim 22, wherein said at least one electron conduction type device and said at least one hole conduction type device are having a device-design which is optimized for device operation between about 250°

K and 70°

K.

24. The strained crystalline layer of claim 22, wherein said strained crystalline layer is hosting at least one bipolar device.

65. The strained crystalline layer of claim 1, wherein at least one crystalline compound semiconductor layer, selected from the group consisting of GaAs, InAs, InP, InSb, SiC, and quaternaries, is epitaxially bonded on top of said strained crystalline layer.

66. The strained crystalline layer of claim 65, wherein said at least one crystalline compound semiconductor layer is hosting at least one optical device.

67. The strained crystalline layer of claim 66, wherein said at least one optical device comprise at least one photodetector.

68. The strained crystalline layer of claim 66, wherein said at least one optical device comprise at least one laser.

69. The strained crystalline layer of claim 7, further comprising an about 0.3 nm to 3 nm thick SiGe first seed layer with up to 25% Ge concentration, wherein said SiGe first seed layer Is epitaxially interposed between said SiGe relaxed buffer and said compressively strained SiGe.

70. The strained crystalline layer of claim 69, wherein said SiGe first seed layer is having up to about 1% C concentration.

71. The strained crystalline layer of claim 8, further comprising an about 0.3 nm to 3 nm thick SiGe second seed layer with up to 25% Ge concentration, wherein said SiGe second seed layer is epitaxially interposed between said SiGe relaxed buffer and said tensilely strained SiGe.

72. The strained crystalline layer of claim 71, wherein said SiGe second seed layer is having up to about 1% C concentration.

73. The strained crystalline layer of claim 15, wherein said tensilely strained SiGe is further hosting at least one optical device.

74. The strained crystalline layer of claim 15, wherein said compressively strained SiGe is further hosting at least one optical device.

25. A layered structure, comprising:

a Si substrate;

an insulating divider layer disposed on top of said substrate, wherein said insulating divider layer comprises at least one metallic plane;

a SiGe relaxed buffer disposed on top of said insulating divider layer; and

a strained crystalline layer epitaxially bonded on top of said SiGe relaxed buffer, said strained crystalline, layer having a tensilely strained SiGe portion and a compressively strained SiGe portion, wherein said tensilely strained SiGe having Ge concentration below that of said SiGe relaxed buffer, and said compressively strained SiGe having Ge concentration above that of said SiGe relaxed buffer.

26. The layered structure of claim 25, wherein said tensilely strained SiGe is having up to about 15% Ge concentration.

27. The layered structure of claim 25, wherein said compressively strained SiGe is having up to about 70% Si concentration.

28. The layered structure of claim 26, wherein said tensilely strained SiGe is having essentially 0% Ge concentration.

29. The layered structure of claim 27, wherein said compressively strained SiGe is having essentially 0% Si concentration.

30. The layered structure of claim 25, wherein said tensilely strained SiGe is having up to about 1% C concentration.

31. The layered structure of claim 25, wherein said compressively strained SiGe is having up to about 1% C concentration.

32. The layered structure of claim 25, wherein said compressively strained SiGe has a graded Ge concentration.

33. The layered structure of claim 25, wherein said strained crystalline layer is between about 0.1 nm and 100 nm thick.

34. The layered structure of claim 33, wherein said strained crystalline layer is between about 0.5 nm and 50 nm thick.

35. The layered structure of claim 25, wherein said SiGe relaxed buffer is between about 0.25 nm and 100 nm thick.

36. The layered structure of claim 35, wherein said SiGe relaxed buffer is between about 5 nm and 60 nm thick.

37. The layered structure of claim 25, wherein said compressively strained SiGe is occupying essentially a plurality of island regions.

38. The layered structure of claim 37, further comprising an about 0.3 nm to 3 nm thick SiGe first seed layer with up to 25% Ge concentration, wherein said SiGe first seed layer is epitaxially interposed between said SiGe relaxed buffer and said compressively strained SiGe.

39. The layered structure of claim 38, wherein said SiGe first seed layer is having up to about 1% C concentration.

40. The layered structure of claim 25, wherein said tensilely strained SiGe is occupying essentially a plurality of island regions.

41. The layered structure of claim 40, further comprising an about 0.3 nm to 3 nm thick SiGe second seed layer with up to 25% Ge concentration, wherein said SiGe second seed layer is epitaxially interposed between said SiGe relaxed buffer and said tensilely strained SiGe.

42. The layered structure of claim 41, wherein said SiGe second seed layer is having up to about 1% C concentration.

43. The layered structure of claim 25, further comprising an isolating trench, wherein said isolating trench separates said tensilely strained SiGe portion and said compressively strained SiGe portion.

44. The layered structure of claim 25, wherein said at least one metallic plane is patterned.

45. The layered structure of claim 25, wherein said at least one metallic plane connects out of said insulating divider layer by means of at least one via.

46. The layered structure of claim 25, wherein an insulating material in said insulating divider layer is selected from the group consisting of a silicon-oxide, a silicon-nitride, an aluminum-oxide, lithium-niobate, a “

low-k”

material, a “

high-k”

material, and combinations of these materials thereof.

47. The layered structure of claim 25, wherein said strained crystalline layer is hosting a plurality of devices, wherein said plurality of devices comprise electron conduction type devices in said tensilely strained SiGe portion, and said plurality of devices comprise hole conduction type devices in said compressively strained SiGe portion.

48. The layered structure of claim 47, wherein at least one of said plurality of electron conduction type devices is an NMOS device and wherein at least one of said plurality of hole conduction type device is a PMOS device.

49. The layered structure of claim 47, wherein said plurality electron conduction type devices and said plurality hole conduction type devices are having a device-design which is optimized for device operation between about 250°

K and 70°

K.

50. The strained crystalline layer of claim 47, wherein said strained crystalline layer is hosting at least one bipolar device.

51. The layered structure of claim 47, wherein said strained crystalline layer is hosting at least one digital circuit.

52. The layered structure of claim 47, wherein said strained crystalline layer is hosting at least one analog circuit.

53. The layered structure of claim 25, wherein said tensilely strained SiGe is further hosting at least one optical device.

54. The layered of claim 25, wherein said compressively strained SiGe is further hosting at least one optical device.

55. The layered structure of claim 54, wherein at least one of said at least one optical device is a photodetector.

56. The layered structure of claim 25, wherein at least one crystalline compound semiconductor layer, selected from the group consisting of GaAs, InAs, InP, InSb, SiC, ternaries, and quaternaries,is epitaxially bonded on top of said strained crystalline layer.

57. The layered structure of claim 56, wherein said at least one crystalline compound semiconductor layer is hosting at least one optical device.

58. The layered structure of claim 57, wherein said at least one optical device comprise at least one photodetector.

59. The layered structure of claim 57, wherein said at least one optical device comprise at least one laser.

63. The layered structure of claim 47, wherein at least one of said plurality of electron conduction type devices is an N-MODFET device.

64. The layered structure of claim 47, wherein at least one of said plurality of hole conduction type device is a P-MODFET device.

60. A processor, comprising:

at least one chip, wherein said chip comprising a strained crystalline layer having a tensilely strained SiGe portion end a compressively strained SiGe portion, wherein said tensilely strained SiGe portion and said compressively strained SiGe portion are in coplanar spatial relation, and said compressively strained SiGe having higher Ge concentration than said tensilely strained SiGe, and the Ge concentration in said compressively strained SiGe is above 90%; and

a plurality of devices in said strained crystalline layer, wherein said plurality of devices comprise electron conduction type devices in said tensilely strained SiGe portion, and said plurality of devices comprise hole conduction type devices in said compressively strained SiGe portion.

61. The processor of claim 60, wherein said processor is a digital processor.

62. The processor of claim 60, wherein said processor comprises at least one analog circuit.

75. A layered structure, comprising:

a Si substrate;

an insulating divider layer disposed on top of said substrate;

a SiGe relaxed buffer disposed on top of said insulating divider layer;

a strained crystalline layer epitaxially bonded on top of said SiGe relaxed buffer, said strained crystalline layer having a tensilely strained SiGe portion and a compressively strained SiGe portion, wherein said tensilely strained SiGe portion and said compressively strained SiGe portion are in coplanar spatial relation, and said tensilely strained SiGe having Ge concentration below that of said SiGe relaxed buffer, and said compressively strained SiGe having Ge concentration above that of said SiGe relaxed buffer; and

at least one crystalline compound semiconductor layer, selected from the group consisting of GaAs, InAs, InP, InSb, and quaternaries, epitaxially bonded on top of said strained crystalline layer.

76. The layered structure of claim 75, wherein said at least one crystalline compound semiconductor layer is hosting at least one optical device.

77. The layered structure of claim 76, wherein said at least one optical device comprise at least one photodetector.

78. The layered structure of claim 76, wherein said at least one optical device comprise at least one laser.

79. A processor, comprising at least one chip, wherein said at least one chip comprising:

a Si substrate;

an insulating divider layer disposed on top of said substrate, wherein said insulating divider layer comprises at least one metallic plane;

a SiGe relaxed buffer disposed on top of said insulating divider layer;

a strained crystalline layer epitaxially bonded on top of said SiGe relaxed buffer, said strained crystalline layer having a tensilely strained SiGe portion and a compressively strained SiGe portion, wherein said tensilely strained SiGe having Ge concentration below that of said SiGe relaxed buffer, and said compressively strained SiGe having Ge concentration above that of said SiGe relaxed buffer; and

a plurality of devices in said strained crystalline layer, wherein said plurality of devices comprise electron conduction type devices in said tensilely strained SiGe portion, and said plurality of devices comprise hole conduction type devices in said compressively strained SiGe portion.

80. A processor, comprising at least one chip, wherein said at least one chip comprising:

a Si substrate;

an insulating divider layer disposed on top of said substrate;

a SiGe relaxed buffer disposed on top of said insulating divider layer;

a strained crystalline layer epitaxially bonded on top of said SiGe relaxed buffer, said strained crystalline layer having a tensilely strained SiGe portion and a compressively strained SiGe portion, wherein said tensilely strained SiGe portion and said compressively strained SiGe portion are in coplanar spatial relation, and said tensilely strained SiGe having Ge concentration below that of said SiGe relaxed buffer, and said compressively strained SiGe having Ge concentration above that of said SiGe relaxed buffer;

at least one crystalline compound semiconductor layer, selected from the group consisting of GaAs, InAs, InP, InSb, and quaternaries, epitaxially bonded on top of said strained crystalline layer; and

a plurality of devices in said strained crystalline layer, wherein said plurality of devices comprise electron conduction type devices in said tensilely strained SiGe portion, and said plurality of devices comprise hole conduction type devices in said compressively strained SiGe portion.