Locking of mold compound to conductive substrate panels

• US 6,963,124 B1
• Filed: 09/17/2004
• Issued: 11/08/2005
• Est. Priority Date: 11/28/2000
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Yeen, Chan Peng, Bayan, Jaime, Nadarajah, Santhiran, Wan, Sharon Ko Mei, Lek, Hu Ah, Spalding, Peter Howard, Hong, Harry Kam Cheng
• Primary Examiner(s): Picardat, Kevin M.
• Application Number:
  US10/943,476
• Time in Patent Office: 417 Days
• Field of Search: 257/678, 257/680, 257/683, 257/685, 257/704, 257/723, 257/731
• US Class Current: 257/678
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/3142 Sealing arrangements between parts, e.g. adhesion promotors
• CPC Class Codes: H01L 23/49548 Cross section geometry H01L23/49562 takes precedence
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/181 Encapsulation

Abstract

A panel assembly of packaged integrated circuit devices including a conductive substrate panel having an array of device areas and a plurality of locking passageways. The locking passageways are positioned about an inactive buffer area which surrounds the periphery of the array of device areas. The panel assembly also includes a molded cap that is molded over the topside of the panel to encapsulate the array of device areas and the inactive buffer area. The molded cap includes conforming locking stem portions that extend into each of the locking passageways in a manner locking the molded cap to the substrate panel such that during singulation of the device areas, the molded cap will not separate from the substrate panel at the inactive buffer area. In another aspect of the invention, a method for producing the panel assembly having the locking passageways is described.

Claims

1. A panel comprising:

a conductive substrate having at least one array of device areas, wherein an inactive buffer area surrounds a peripheral edge of each array of device areas, a plurality of locking passageways being positioned within each inactive buffer are each of the locking passageways extending from a topside of the substrate towards a bottom side thereof,

wherein a position of the locking passageways are suitable for receiving a locking stem of a molding cap that covers at least one array of device areas, such that contact between each of the locking stems and locking passageways locks the molded cap to the conductive substrate, wherein a portion of the molded cap will not separate from the conductive substrate when the device areas are singulated.

2. The panel as recited in claim 1 wherein each locking passageway includes a lock section having a transverse cross-sectional dimension larger than that at a topside entrance into the respective locking passageway such that a corresponding lock section of a corresponding stem of a molded cap has a larger transverse cross-sectional dimension than a corresponding section of the stem at the topside entrance into the passageway.

3. The panel as recited in claim 1 wherein at least one of the locking passageways defines a transverse cross-sectional area substantially having the shape of an elongated oval, a circle, a square or an “

L”

.

4. The panel as recited in claim 1 wherein at least two of the locking passageways are grouped together such that the at least two locking passageways are positioned proximate to each other.

5. The panel as recited in claim 1 wherein each of the device areas contains a semiconductor die, a plurality of electrical contacts positioned adjacent to the semiconductor die, and a plurality of interconnecting wires that connect the semiconductor die to each of the electrical contacts.

6. The panel as recited in claim 1 wherein the locking passageways extend from the substrate topside to the substrate bottom side thereof.

7. The panel as recited in claim 6 wherein each locking passageway has a bottom side entrance that has a cross-sectional dimension larger than that of a topside entrance such that a corresponding locking stem has a cross-sectional dimension at the bottom side entrance that is larger than a cross-sectional dimension at the topside entrance.

8. The panel as recited in claim 1 wherein each locking passageway has its smallest width dimension located at some point in between the substrate topside and the substrate bottom side such that each locking passageway has an hourglass shape.

9. A panel comprising:

a conductive substrate having at least one array of device areas, wherein an inactive buffer area surrounds a peripheral edge of each array of device areas, a plurality of locking passageways being positioned within each inactive buffer area, each of the locking passageways extending from a topside of the substrate towards a bottom side thereof, wherein each locking passageway includes a lock section and a topside entrance, a diameter of the locking passageway at the lock section being larger than a diameter at the topside entrance.

10. The panel as recited in claim 9 wherein at least one of the locking passageways defines a transverse cross-sectional area substantially having the shape of an elongated oval, a circle, a square or an “

L”

.

11. The panel as recited in claim 9 wherein at least two of the locking passageways are groped together such that the at least two locking passageways are positioned proximate to each other.

12. The panel as recited in claim 9 wherein each of the device areas contains a semiconductor die, a plurality of electrical contacts positioned adjacent to the semiconductor die, and a plurality of interconnecting wires that connect the semiconductor die to each of the electrical contacts.

13. The panel as recited in claim 9 wherein the locking passageways extend from the substrate topside to the substrate bottom side thereof.

14. The panel as recited in claim 13 wherein each locking passageway has a bottom side entrance that has a cross-sectional dimension larger than that of a topside entrance such that a corresponding locking stem has a cross-sectional dimension at the bottom side entrance that is larger than a cross-sectional dimension at the topside entrance.

15. The panel as recited in claim 9 wherein each locking passageway has its smallest width dimension located at some point in between the substrate topside and the substrate bottom side such that each locking passageway has an hourglass shape.

16. A panel comprising:

a conductive substrate having at least one array of device areas, and defining a plurality of locking passageways positioned about an inactive buffer area that peripherally surrounds the array of device areas, the locking passageways extending from a topside of the substrate toward a bottom side thereof, wherein when a molded cap is molded over the substrate topside to encapsulate the device areas of the array and the inactive buffer area, a conforming locking stem portion is integrally formed with the molded cap and extends into each locking passageway such that each of the locking stains have substantially the same shape and size as the locking passageway into which each of the locking stems extend, the locking stems configured to lock the molded cap to the substrate such that during singulation of the device areas, the molded cap will not separate from the substrate at the inactive buffer area.

17. The panel as recited in claim 16 wherein each locking passageway includes a lock section having a transverse cross-sectional dimension larger that at a topside entrance into the respective locking passageway such that a corresponding lock section of the corresponding stem has a larger transverse cross-sectional dimension than a corresponding section of the stem at the topside entrance into the locking passageway.

18. The panel as recited in claim 16 wherein at least one of the locking passageways defines a transverse cross-sectional area substantially having the shape of an elongated oval, a circle, a square or an “

L”

.

19. The panel as recited in claim 16 wherein the locking passageways extend from the substrate topside to the substrate bottom side thereof.

20. The panel as recited in claim 19 wherein each locking passageway has a bottom side entrance that has a cross-sectional dimension larger than that of a topside entrance such that a corresponding stem having a cross-sectional dimension at the bottom side entrance that is larger than a cross-sectional dimension at the topside entrance.

21. The panel as recited in claim 19 wherein each locking passageway has its smallest width dimension located at a point in between the topside and the bottom side of the conductive substrate.

22. A pal as recited in claim 21, wherein each locking passageway has an hourglass shape.