Internal power supply voltage generation circuit that can suppress reduction in internal power supply voltage in neighborhood of lower limit region of external power supply voltage

• US 6,963,230 B2
• Filed: 11/15/2001
• Issued: 11/08/2005
• Est. Priority Date: 02/16/1998
• Status: Expired due to Fees

• Current Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Morishita, Fukashi
• Primary Examiner(s): Cunningham, Terry D.
• Application Number:
  US09/987,566
• Publication Number:
  US 20020030538A1
• Time in Patent Office: 1,454 Days
• Field of Search: 327/53, 327/56, 327/63, 327/65, 327/66, 327/77, 327/89, 327/563
• US Class Current: 327/77
• CPC Class Codes: G05F 1/465 Internal voltage generators for integrated circuits, e.g. step down generators

Abstract

An internal power supply voltage generation circuit includes a main amplifier that supplies a current from an external power supply node to an internal power supply line in accordance with the difference between a reference voltage from a reference voltage generation circuit and an internal power supply voltage on the internal power supply line. The current supply amount by the main amplifier is adjusted by a level adjust circuit, according to the difference between the external power supply voltage and the reference voltage. The internal power supply voltage generation circuit can suppress reduction in the internal power supply voltage in the vicinity of the lower limit area of the differential power supply voltage.

Claims

1. Level detection circuitry for detecting a difference between a first voltage and a second voltage, comprising:

a differential stage including a first insulated gate transistor and a second insulated gate transistor,

said first insulated gate transistor receiving a power supply voltage as the first voltage at a gate thereof and having a first conduction node, and a second conduction node for outputting a difference signal, and

said second insulated gate transistor receiving a reference voltage as the second voltage at a gate thereof and having a first conduction node connected to said first conduction node of said first insulated gate transistor, said second insulated gate transistor having a current supply ability different from a current supply ability of said first insulated gate transistor under a condition of the same gate voltage, and said difference signal corresponding to a difference between the first and second voltages, said reference voltage determining a voltage level of an internal voltage generated from said power supply voltage;

operation current supply circuitry for supplying an operation current to the first and second insulated gate transistors, said operation current supply circuitry comprising a current mirror coupled to the first and second insulated gate transistors for supplying current to the first and second insulated gate transistors; and

a buffer circuit for buffering said difference signal for generating a binary level detection signal indicating whether said first voltage is higher than said second voltage.

2. The level detection circuitry according to claim 1, wherein said first insulated gate transistor is smaller in channel width than said second insulated gate transistor.