Analog to digital converter with voltage comparators that compare a reference voltage with voltages at connection points on a resistor ladder

• US 6,963,298 B2
• Filed: 05/23/2002
• Issued: 11/08/2005
• Est. Priority Date: 08/30/2001
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi ULSI Systems Company Limited (Hitachi, Ltd.), Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Yamakido, Kazuo, Sano, Shinya, Otsuka, Masanori, Yamamoto, Etsuji
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): Mai, Lam T.
• Application Number:
  US10/152,638
• Publication Number:
  US 20030043066A1
• Time in Patent Office: 1,265 Days
• Field of Search: 341/155, 341/156, 341/133, 341/172, 341/160, 341/118, 341/103, 341/159, 341/161
• US Class Current: 341/155
• CPC Class Codes: H03M 1/363 the voltage divider taps being held in a floating state, e.g. by feeding the divider by current sources

Abstract

An AD converter which uses no buffer for receiving the input signals or uses the buffer having relaxed requirements concerning the range of input signals and the output impedance. Voltage at the connection points of a resistor ladder in which a plurality of resistor elements are connected in series, are compared with a reference voltage by a plurality of voltage comparators, a first current circuit is provided on the high potential side of the resistor ladder, a second current circuit is provided on the low potential side thereof, and analog input voltages are fed by providing an input terminal at any place of the resistor ladder except both ends thereof.

Claims

1. An AD converter comprising:

a resistor ladder including a plurality of resistor elements connected in series between a high potential node and a low potential node;

a plurality of voltage comparators that compare a reference voltage with voltages at connection points where the resistor elements of the resistor ladder are connected to each other;

a first current circuit coupled to a high potential side of the resistor ladder;

a second current circuit coupled to a low potential side of the resistor ladder; and

an input terminal provided at one of the connection points to receive an analog input voltage.

2. An AD converter according to claim 1, wherein a current value of the first current circuit and a current value of the second current circuit are set to be equal to each other by current mirror circuits.

3. An AD converter according to claim 1, wherein the resistor ladder is constituted by 2ⁿ resistor elements, and there are 2ⁿ−

1 voltage comparators corresponding to the connection points where the resistor elements are connected to each other, thereby to form n-bit digital signals.

5. An AD converter according to claim 1, wherein the input terminal is provided at a center of the resistor ladder or at the connection point near the center thereof.

6. An AD converter according to claim 1, wherein a capacitor element is provided between the input terminal and a predetermined connection point of the resistor ladder.

7. An AD converter according to claim 1, wherein a track-holding circuit is provided for the input terminal.

4. An AD converter comprising:

a resistor ladder including a plurality of unit resistor elements connected in series between a high potential node and a low potential node;

a plurality of voltage comparators that compare a reference voltage with voltages at connection points where the unit resistor elements of the resistor ladder are connected to each other;

a first current circuit coupled to a high potential node of the resistor ladder and a second current circuit connected to a low potential node of the resistor ladder; and

an input terminal provided at one of the connection points to receive an analog input voltage,

wherein the resistor ladder includes 2ⁿ unit resistor elements, and resistor elements at both ends of the resistor ladder have a resistance value one-half of the resistance value of a unit resistor element,

wherein there are 2ⁿ voltage comparators corresponding to the connection points where the unit resistor elements and the resistor elements at both ends of the resistor ladder are coupled, thereby to form n-bit digital signals.

8. An AD converter comprising:

a first resistor ladder including 2ⁿ unit resistor elements coupled in series between a high potential side and a low potential side;

a second resistor ladder including 2ⁿ unit resistor elements coupled in series between the high potential side and the low potential side;

2ⁿ−

1 comparators;

first connection points where the unit resistor elements of the first resistor ladder are coupled to each other;

second connection points where the unit resistor elements of the second resistor ladder are coupled to each other;

a first current circuit coupled to the high potential side of the first resistor ladder;

a second current circuit coupled to the low potential side of the first resistor ladder;

a third current circuit coupled to the high potential side of the second resistor ladder; and

a fourth current circuit coupled to the low potential side of the second resistor ladder;

wherein there are 2ⁿ−

1 first connection points,

wherein there are 2ⁿ−

1 second connection points,

wherein the k-th comparator (1≦

k≦

2ⁿ−

1) compares the k-th first connection point counted from the high potential side of the first resistor ladder with the k-th second connection point counted from the low potential side of the second resistor ladder,

wherein the first resistor ladder includes a positive-phase analog input terminal at a predetermined place of the first connection point, and

wherein the second resistor ladder includes a negative-phase analog input terminal at a predetermined place of the second connection point;

thereby to form n-bit digital signals.

9. An AD converter according to 8,

wherein a current value of the first current circuit and a current value of the second current circuit are set to be equal to each other by current mirror circuits, and

wherein a current value of the third current circuit and a current value of the fourth current circuit are set to be equal to each other by current mirror circuits.

10. AD converter according to claim 8, wherein the positive phase analog input terminal is the 2ⁿ⁻

1-th second connection point counted from the high potential side of the first resistor ladder, and

wherein the negative phase analog input terminal is the 2<sup>n−

1</sup>-th second connection point counted from the high potential side of the second resistor ladder.