API communications for vertex and pixel shaders

• US 6,963,345 B2
• Filed: 11/04/2004
• Issued: 11/08/2005
• Est. Priority Date: 03/07/2000
• Status: Expired due to Term

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Corporation
• Inventors: Toelle, Michael A., Boyd, Charles N.
• Primary Examiner(s): Bella, Matthew C.
• Assistant Examiner(s): NGUYEN, HAU H
• Application Number:
  US10/981,353
• Publication Number:
  US 20050128207A1
• Time in Patent Office: 369 Days
• Field of Search: 345/559, 345/426, 345/519, 345/552, 345/561, 345/537, 345/538, 345/643, 345/501, 345/522
• US Class Current: 345/559
• CPC Class Codes: G06T 15/00 3D [Three Dimensional] image rendering
• CPC Class Codes: G06T 15/005 General purpose rendering architectures
• CPC Class Codes: G06T 15/80 Shading
• CPC Class Codes: G06T 2210/32 Image data format

Abstract

A three-dimensional API for communicating with hardware implementations of vertex shaders and pixel shaders having local registers. With respect to vertex shaders, API communications are provided that may make use of an on-chip register index and API communications are also provided for a specialized function, implemented on-chip at a register level, that outputs the fractional portion(s) of input(s). With respect to pixel shaders, API communications are provided for a specialized function, implemented on-chip at a register level, that performs a linear interpolation function and API communications are provided for specialized modifiers, also implemented on-chip at a register level, that perform modification functions including negating, complementing, remapping, stick biasing, scaling and saturating. Advantageously, these API communications expose these very useful on-chip graphical algorithmic elements to a developer while hiding the details of the operation of the vertex shader and pixel shader chips from the developer.

Claims

1. A computer-readable medium having computer-executable instructions for communicating between a 3-D graphics API of a host computing system having a main memory stack and a 3-D graphics hardware rendering device having on-chip register storage, wherein the computer-executable instructions perform:

receiving at least one instruction having at least one graphics data argument by the 3-D API;

formatting said at least one instruction for the register storage of the hardware rendering device;

providing said at least one formatted instruction to the hardware rendering device;

processing said at least one graphics data argument, pursuant to said at least one formatted instruction, by the hardware rendering device without accessing the main memory stack of the host computing system;

outputting the result of said processed at least one graphics data argument from said hardware rendering device in accordance with said at least one formatted instruction;

wherein said at least one instruction is an instruction with at least one floating point number argument and said outputting includes outputting from the hardware rendering device the fractional portion of said at least one floating point number; and

wherein said outputting includes outputting four fractional portions of corresponding four floating point number arguments.

2. The computer-readable medium of claim 1, wherein said formatting includes remapping to the register state of register storage.

3. The computer-readable medium of claim 1, wherein the computer-executable instructions perform communicating said at least one instruction directly to said hardware rendering device, thereby bypassing the main memory stack of the host computing system.

4. The computer-readable medium of claim 1, wherein said processing of said at least one graphics data argument includes performing at least one of reading from and writing to the on-chip register storage.

5. The computer-readable medium of claim 1, wherein the computer-executable instructions perform storing a register index in the on-chip register storage.

6. The computer-readable medium of claim 5, wherein the computer-executable instructions perform accessing the register index stored in the on-chip register storage and finding another register of the register storage to be used incident to carrying out said at least one instruction by said hardware rendering device.

7. The computer-readable medium of claim 1, wherein said hardware rendering device includes a processor and an arithmetic/logic unit that aid in the performance of said processing.

8. The computer-readable medium of claim 1, wherein said at least one instruction is an instruction with a plurality of floating point number arguments and said processing includes processing the plurality of floating point number arguments to calculate a number representative of a linear interpolation between two of the floating point number arguments.

9. The computer-readable medium of claim 1, wherein said at least one instruction is an instruction with a plurality of floating point number arguments and said outputting includes outputting a floating point number representative of a linear interpolation between two of the floating point number arguments.

10. The computer-readable medium of claim 1, wherein said at least one instruction includes a special modifier function to be performed during said processing of the graphics data by the hardware rendering device.

11. The computer-readable medium of claim 10, wherein said special modifier function performed during said processing is at least one of a negating modifier, complementing modifier, remapping modifier, stick biasing modifier, saturating modifier and scaling modifier.

12. A computer system for communicating with 3-D graphics hardware, comprising:

a 3-D graphics API;

a host computing system having a main memory stack;

a 3-D graphics hardware rendering device having on-chip register storage, wherein at least one instruction having at least one graphics data argument is received by the 3-D API, and wherein said at least one instruction for the register storage is formatted and provided to the hardware rendering device, and wherein said at least one graphics data argument is processed pursuant to said at least one formatted instruction, by the hardware rendering device without accessing the main memory stack of the host computing system;

an output for providing the result of said processed at least one graphics data argument from said hardware rendering device in accordance with said at least one formatted instruction, wherein said at least one instruction is an instruction with at least one floating point number argument and said output includes outputting from the hardware rendering device the fractional portion of said at least one floating point number, and wherein said output includes outputting four fractional portions of corresponding four floating point number arguments.

13. The computer system of claim 12, wherein said formatting includes remapping to the register state of register storage.

14. The computer system of claim 12, wherein said at least one instruction is communicated directly to said hardware rendering device, thereby bypassing the main memory stack of the host computing system.

15. The computer system of claim 12, wherein said processing of said at least one graphics data argument includes performing at least one of reading from and writing to the on-chip register storage.

16. The computer system of claim 12, further comprising a register index that is stored in the on-chip register storage.

17. The computer system of claim 16, wherein the register index stored in the on-chip register storage is accessed and finding another register of the register storage to be used incident to carrying out said at least one instruction by said hardware rendering device.

18. The computer system of claim 12, wherein said hardware rendering device includes a processor and an arithmetic/logic unit that aid in the performance of said processing.

19. The computer system of claim 12, wherein said at least one instruction is an instruction with a plurality of floating point number arguments and said processing includes processing the plurality of floating point number arguments to calculate a number representative of a linear interpolation between two of the point number arguments.

20. The computer system of claim 12, wherein said at least one instruction is an instruction with a plurality of floating point number arguments and said outputting includes outputting a floating point number representative of a linear interpolation between two of the floating point number arguments.

21. The computer system of claim 12, wherein said at least one instruction includes a special modifier function to be performed during said processing of the graphics data by the hardware rendering device.

22. The computer system of claim 21, wherein said special modifier function performed during said processing is at least one of a negating modifier, complementing modifier, remapping modifier, stick biasing modifier, saturating modifier and scaling modifier.