Method circuit and system for determining a reference voltage

• US 6,963,505 B2
• Filed: 10/29/2003
• Issued: 11/08/2005
• Est. Priority Date: 10/29/2002
• Status: Expired due to Term

• Current Assignee: Spansion Israel Limited (Infineon Technologies AG)
• Original Assignee: Aifun Semiconductors Limited
• Inventors: Cohen, Guy
• Primary Examiner(s): MAI, SON LUU
• Application Number:
  US10/695,448
• Publication Number:
  US 20040136220A1
• Time in Patent Office: 741 Days
• Field of Search: 365/185.03, 365/185.2, 365/201, 365/210
• US Class Current: 365/185.03
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 16/3436 Arrangements for verifying correct programming or erasure
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 2029/4402 Internal storage of test result, quality data, chip identification, repair information
• CPC Class Codes: G11C 2029/5004 Voltage
• CPC Class Codes: G11C 2211/5634 Reference cells
• CPC Class Codes: G11C 29/24 Accessing extra cells, e.g. dummy cells or redundant cells
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing

Abstract

The present invention is a method, circuit and system for determining a reference voltage. Some embodiments of the present invention relate to a system, method and circuit for establishing a set of operating reference cells to be used in operating (e.g. reading) cells in an NVM block or array. As part of the present invention, at least a subset of cells of the NVM block or array may be read using each of two or more sets of test reference cells, where each set of test reference cells may generate or otherwise provide reference voltages at least slightly offset from each other set of test reference cells. For each set of test reference cells used to read at least a subset of the NVM block, a read error rate may be calculated or otherwise determined. A set of test reference cells associated with a relatively low read error rate may be selected as the set of operating reference cells to be used in operating (e.g. reading) other cells, outside the subset of cells, in the NVM block or array. In a further embodiment, the selected set of test reference cells may be used to establish an operating set of reference cells having reference voltages substantially equal to those of the selected test set.

Claims

1. A method of selecting a reference level from a set of possible reference levels, comprising:

using each of said possible reference levels to read a set of cells from a memory area;

determining a read error rate for each one of said possible reference levels associated with the reading of said set of cells; and

selecting a reference level from said set of possible reference levels whose read error rate is relatively low.

2. The method of claim 1, wherein said selecting comprises choosing a reference level from said set of possible reference levels resulting in the lowest read error rate.

3. The method of claim 1, wherein said selecting comprises choosing a reference level from said set of possible reference levels resulting in a read error rate that is below a predetermined threshold.

4. The method of claim 1, wherein each reference level from said set of possible reference levels is slightly different from each of the other reference voltages in said set.

5. The method of claim 4, wherein said set of possible reference levels comprises incrementally changing reference levels.

6. The method of claim 4, wherein said set of possible reference levels comprises incrementing reference levels in constant increments.

7. The method of claim 4, wherein said set of possible reference levels comprises incrementally changing reference levels in changing increments.

8. The method of claim 1, further comprising repeating each of said using, determining and selecting for each verify level of said memory states.

9. The method of claim 6, further comprising using a different set of possible reference levels for each state of said memory area.

10. The method of claim 6, further comprising using a different set of possible reference levels for each state of said memory area simultaneously.

11. The method of claim 1, further comprising repeating each of said using, determining and selecting for each charge storage region of one or more memory cells.

12. The method of claim 8, wherein said repeating comprises repeating each of said using, determining and selecting for each charge storage region of one or more NROM memory cells.

13. A method of establishing a reference cell based on a selected reference voltage, comprising:

determining a read error rate associated with each possible reference voltage from a set of possible reference voltages;

selecting a reference voltage from said set of possible reference voltages resulting in a relatively low read error rate; and

establishing a reference cell based on said selected reference voltage.

14. The method of claim 13, wherein said establishing comprises:

comparing said selected reference voltage to each of a plurality of reference cells from a bank of reference cells; and

selecting a reference cell from said bank of reference cells having a relatively low read error rate.

15. The method of claim 14, wherein said selecting comprises choosing a reference cell from said bank of reference cells having the lowest read error rate.

16. The method of claim 14, wherein said error rate is representative of the correlation between said reference voltage and the threshold voltage of each of said reference cells.

17. The method of claim 16, wherein each of said reference cells is configured to have a slightly different threshold voltage.

18. The method of claim 17, wherein the threshold voltage of each of said reference cells is incrementally changing.

19. The method of claim 14, wherein said determining, said selecting and said establishing may be repeated for each state of a Multi Level Cell.

20. The method of claim 13, wherein said determining, said selecting and said establishing may be perform simultaneously for each state of a Multi Level Cell.

21. The method of claim 19, wherein for each repeat of said determining, said selecting and said establishing a distinct set of reference voltages is used.

22. The method of claim 13, wherein said establishing comprises adapting an offset circuit such that said set of possible reference voltages in combination with an offset value may be substantially equal to said selected reference voltage. [no support in the spec. for effective gate voltage;

paragraph 37 provides support for the amended claim]

23. The method of claim 22, wherein said adapting comprises:

receiving an input signal to be associated with said selected reference voltage;

processing said input signal to determine an offset value associated with said selected reference voltage; and

offsetting a voltage to be applied to the reference cell in accordance with said offset value.

24. The method of claim 23, wherein said processing comprises calculating said offset value to indicate to said offset circuit to offset an input voltage by said offset value, such that said set of possible reference voltages to be applied to said reference cell is substantially equal to the reference voltage of said reference cell.

25. The method of claim 24, wherein said offsetting comprises offsetting an input that is substantially equal to said selected reference voltage, such that said set of possible reference voltages is substantially equal to the threshold voltage of said reference cell.

26. The method of claim 13, wherein said establishing comprises programming said reference cell such that the threshold voltage of the reference cell is substantially equal to said selected reference voltage.

27. The method of claim 26, wherein said programming comprises programming said selected reference voltage into said reference cell.

28. The method of claim 27, wherein said programming comprises programming one of a set of preselected programming values into said reference cell.

29. A method of operating a memory array based on a selected reference voltage, comprising:

determining a read error rate associated with one or more possible reference voltages from a set of possible reference voltages;

selecting a reference voltage from said set of possible reference voltages resulting in a relatively low error rate;

establishing a reference cell based on said selected reference voltage; and

operating said memory array using said established reference cell.

30. The method of claim 29, wherein said operating comprises reading at least one memory cell from said memory array using said established memory cell.

31. The method of claim 29, wherein selecting a reference voltage from the set of possible reference voltages is done prior to determining a read error rate for all of the possible sets of reference voltages.

32. The method according to claim 31, wherein a first reference voltage associated with an error rate below a predefined threshold value is selected.

33. The method according to claim 29, wherein the cell operated is selected from the group consisting of non-volatile memory (“

NVM”

) cells, and NVM Multi-Level Cell (“

MLC”

).

34. The method according to claim 29, further comprising storing a plurality of error detection rates in close proximity to the memory cells.

35. The method according to claim 29, further comprising storing a plurality of selected reference values in close proximity to the memory cells.