Fabrication method of semiconductor device
First Claim
1. A method of fabricating a semiconductor device, comprising the steps of:
- (a) forming a logic circuit and an electrically reprogrammable ROM circuit each having substantially the same structure in each of first and second chip areas on a wafer;
(b) discretely or simultaneously executing a first electrical operation test on the first and second chip areas (c) after said step (b), respectively electrically writing first and second ROM pattern data corresponding to first and second user'"'"'s uses into the ROM circuits in the first and second chip areas respectively, as a step prior to or below the first electrical operation test;
(d) dividing the wafer into the first and second chip areas after said step (c); and
(e) executing a second electrical operation test on the divided first and second chip areas respectively.
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Accused Products
Abstract
The present invention provides a technology capable of shortening a TAT of a microcomputer with a nonvolatile memory built therein and achieving a reduction in cost. Flash ROMs comprising memory cells each substantially identical in structure to each of memory cells of a flash memory are formed in their corresponding chips lying in a wafer. Subsequently, memory information is written into each of the memory cells of the flash ROM in a probe test process. Thereafter, the memory information written into the memory cell thereof is made unreprogrammable to thereby disable rewriting of the post-shipment memory information. Thus, the shortening of a TAT can be achieved as compared with a mask ROM built-in microcomputer, and management and fabrication costs can be reduced.
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Citations
9 Claims
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1. A method of fabricating a semiconductor device, comprising the steps of:
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(a) forming a logic circuit and an electrically reprogrammable ROM circuit each having substantially the same structure in each of first and second chip areas on a wafer;
(b) discretely or simultaneously executing a first electrical operation test on the first and second chip areas (c) after said step (b), respectively electrically writing first and second ROM pattern data corresponding to first and second user'"'"'s uses into the ROM circuits in the first and second chip areas respectively, as a step prior to or below the first electrical operation test;
(d) dividing the wafer into the first and second chip areas after said step (c); and
(e) executing a second electrical operation test on the divided first and second chip areas respectively. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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Specification
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- Resources
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Current AssigneeRenesas Electronics Corporation
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Original AssigneeRenesas Technology Corporation (Renesas Electronics Corporation)
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InventorsYamamoto, Toshitaka, Satou, Shouji
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Primary Examiner(s)Nguyen, Viet Q.
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Application NumberUS10/919,350Publication NumberTime in Patent Office448 DaysField of Search365/201, 365/51, 365/94US Class Current365/201CPC Class CodesG11C 16/22 Safety or protection circui...G11C 17/10 in which contents are deter...G11C 2216/26 Floating gate memory which ...H10B 20/00 Read-only memory [ROM] devicesH10B 20/25 One-time programmable ROM [...H10B 20/34 Source electrode or drain e...H10B 41/30 characterised by the memory...
