Microwire dynamic sequencer pipeline stall

• US 6,963,554 B1
• Filed: 12/27/2000
• Issued: 11/08/2005
• Est. Priority Date: 12/27/2000
• Status: Active Grant

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Weigand, David
• Primary Examiner(s): VINCENT, DAVID ROBERT
• Application Number:
  US09/751,152
• Time in Patent Office: 1,777 Days
• Field of Search: 710/260, 710261-269, 710 33- 36, 710/58, 710/1, 370/311, 370/321, 370/337, 370347-348, 370/442, 370/458, 711 1- 5, 711100-104, 711200-201, 712/1, 712/32, 712 34- 36, 712 42- 43, 712203-205, 712230-231, 712242-245
• US Class Current: 370/347
• CPC Class Codes: G06F 9/30083 Power or thermal control instructions
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units

Abstract

A Time Division Multiple Access (TDMA) mobile station architecture consuming less power and random access memory (RAM) is presented herein. The mobile station includes a system timer coprocessor which includes a microsequencer and a microwire for controlling radio components. Responsive execution of a single instruction by the microsequencer, the microwire transmits multiple bytes to the radio components. While the microwire transmits multiple bytes, execution of additional instructions for the microwire to transmit bytes is prevented by dynamically stalling the microsequencer pipeline.

Claims

1. A system for controlling radio components, said system comprising:

a microcode random access memory for storing a frame program, said frame program comprising a certain instruction;

a microsequencer for executing the certain instruction;

a microwire for transmitting a predetermined number of bytes to the radio components, responsive to the microsequencer executing the certain instruction; and

a delay unit for selectively delaying the microsequencer by a predetermined period of time, responsive to the microsequencer executing the certain instruction;

wherein

the certain instruction comprises a value indicative of the predetermined number of bytes,

the value is indicative of the predetermined period of time, and

the predetermined period of time is the value minus one.

2. A system for controlling radio components, said system comprising:

a microcode random access memory for storing a frame program, said frame program comprising a certain instruction;

a microsequencer for executing the certain instruction;

a microwire for transmitting a predetermined number of bytes to the radio components, responsive to the microsequencer executing the certain instruction;

a delay unit for selectively delaying the microsequencer by a predetermined period of time, responsive to the microsequencer executing the certain instruction; and

a microwire random access memory for storing the predetermined number of bytes at a particular address;

wherein

the certain instruction comprises a value indicative of the predetermined number of bytes,

the certain instruction comprises the particular address, and

the predetermined period of delay is the value minus one if the particular address is odd.

3. A method for controlling radio components, said method comprising:

executing a certain instruction;

transmitting a predetermined number of bytes to the radio components, responsive to executing the certain instruction; and

selectively preventing execution of other instructions for a predetermined period of time, responsive to executing the certain instruction;

wherein

the certain instruction comprises a value indicative of the predetermined number of bytes,

the value is indicative of the predetermined period of time, and

the predetermined period of time is the value minus one.

4. A method for controlling radio components, said method comprising:

executing a certain instruction;

transmitting a predetermined number of bytes to the radio components, responsive to executing the certain instruction; and

selectively preventing execution of other instructions for a predetermined period of time, responsive to executing the certain instruction;

wherein

the certain instruction comprises a value indicative of the predetermined number of bytes,

the certain instruction comprises a particular memory address

transmitting a predetermined number of bytes further comprises transmitting the predetermined number of bytes beginning at the particular memory address,

the value and the particular memory address are indicative of the predetermined period of time, and

the predetermined period of delay is the value minus one if the particular memory address is odd.