Noise-reducing arrangement and method for signal processing

• US 6,963,626 B1
• Filed: 05/12/1999
• Issued: 11/08/2005
• Est. Priority Date: 10/02/1998
• Status: Expired due to Fees

• Current Assignee: Stanford University
• Original Assignee: Board of Trustees of the Leland Stanford Junior University (Stanford University)
• Inventors: Shaeffer, K. Derek, Reader, Sydney, Meng, Theresa H., Lee, Thomas H.
• Primary Examiner(s): Tran, Khai
• Assistant Examiner(s): Lugo, David B.
• Application Number:
  US09/310,598
• Time in Patent Office: 2,372 Days
• Field of Search: 375/216, 375/346, 375/340, 375/350, 455/343.1, 455/343.4, 455/574
• US Class Current: 375/346
• CPC Class Codes: H04B 1/0475 with means for limiting noise, interference or distortion H04B1/0483 takes precedence
• CPC Class Codes: H04B 1/30 for homodyne or synchrodyne receivers demodulator circuits H03D1/22

Abstract

A communication system uses analog and digital circuits along the same data path in a manner that permits the analog circuitry to avoid adverse affects caused by the digital circuitry. Consistent with one embodiment directed to a signal processing system that detects faint incoming signals, the analog and digital circuits are implemented on a single piece of silicon. In such signal processing systems, noise generated by digital processing blocks can degrade the performance of sensitive analog portions. The effective noise is reduced by causing the analog and digital portions of the system to function during separate time intervals. The noise-generating portions of the system may then be turned off during a first data-communication interval while the analog block operates. The data acquired during this period is stored for subsequent processing by the digital portion during a second shorter data-communication interval. Other aspects are applicable to reception arrangements in which part of the incoming signal may be disregarded without significant degradation in performance of the rest of the system, and other aspects are directed to transmission arrangements in which the inverse of the above reception arrangement is used.

Claims

1. In a communication arrangement having analog circuitry and having digital signal processing circuitry clocked sufficiently fast to generate noise, the analog circuitry susceptible to processing corrupted data due to the noise coupled thereto, a method for reducing noise passed from the digital signal processing circuitry, comprising the steps of:

using the analog circuitry to capture information data from an incoming stream for a first time interval while the digital signal processing circuitry is in a reduced-activity mode; and

in a mode other than the reduced-activity mode occurring during a known guard time for the data being communicated to the communication arrangement and during a second shorter time interval, clocking the digital signal processing circuitry to permit digital signal processing of the captured information data.

2. A method for reducing noise passed from the digital signal processing circuitry, according to claim 1, further including the step of providing both the analog circuitry and the digital signal processing circuitry on the same chip, and wherein the step of using the analog circuitry to process data includes receiving the data in the form of low-energy data.

3. A method for reducing noise passed from the digital signal processing circuitry, according to claim 1, wherein the step of using the analog circuitry to process data includes receiving the data in the form of low-energy data and storing the data in a memory circuit.

4. A method for reducing noise passed from the digital signal processing circuitry, according to claim 3, further including inhibiting the analog circuitry from storing data in a memory circuit.

5. A communication arrangement having analog circuitry and digital signal processing circuitry, the analog circuitry susceptible to processing corrupted data due to noise coupled thereto via digital signal processing circuitry, an arrangement for reducing noise passed from the digital signal processing circuitry, comprising:

means for using the analog circuitry to process data during a first data-communication interval while the digital signal processing circuitry is in a reduced activity mode; and

means for effectively disabling the processing of data by the analog circuitry during a second shorter data-communication interval and during a known guard time for the data being communicated to the communication arrangement while processing the data with the digital signal processing circuitry.

6. A communication arrangement, according to claim 5, further including a single chip carrying the analog circuitry and the digital signal processing circuitry.

7. A communication arrangement, according to claim 5, further including a memory circuit arranged to store data processed by the analog circuitry while the digital signal processing circuitry is in a reduced activity mode.

8. A communication arrangement, according to claim 7, wherein the memory circuit is part of the means for using the analog circuitry to process data while the digital signal processing circuitry is in a reduced activity mode.

9. A communication arrangement, according to claim 7, wherein the memory circuit is distinct from the means for using the analog circuitry to process data while the digital signal processing circuitry is in a reduced activity mode.

10. A communication arrangement, according to claim 5, wherein the means for using the analog circuitry to process data while the digital signal processing circuitry is in a reduced activity mode includes means for receiving low-energy, high-frequency data.

11. A communication arrangement, according to claim 5, wherein the means for using the analog circuitry to process data while the digital signal processing circuitry is in a reduced activity mode includes means for transmitting data.

12. A communication arrangement susceptible to processing corrupted data due to noise coupled thereto via high-speed data processing, comprising:

a chip including both digital signal processing circuitry and analog circuitry, the digital signal processing circuitry having a reduced activity mode and a high-speed data processing mode, and the analog circuitry configured and arranged to capture and process data during a first data-communication interval while the digital signal processing circuitry is in the reduced activity mode; and

means for effectively disabling the capture and processing of data by the analog circuitry during a known guard time for the data being communicated to the communication arrangement and during a second shorter data-communication interval while processing the data with the digital signal processing circuitry.

13. A communication arrangement, according to claim 12, wherein the chip further includes the means for effectively disabling the processing of data.

14. A communication arrangement, according to claim 12, wherein digital signal processing circuitry and analog circuitry are configured and arranged to receive data.

15. A communication arrangement, according to claim 12, wherein digital signal processing circuitry and analog circuitry are configured and arranged to receive and transmit data.

16. A communication arrangement, according to claim 12, wherein both digital signal processing circuitry and analog circuitry are configured and arranged to transmit data.

17. In a communication arrangement having analog circuitry and digital signal processing circuitry, the analog circuitry coupled to receive streams of data presented thereto in the form of high-frequency signals for subsequent processing by the digital signal processing circuitry, a method for reducing noise passed from the digital signal processing circuitry to the data, comprising the steps of:

using the analog circuitry to process and to store the data during a first data-communication interval while the digital signal processing circuitry is in a reduced activity mode; and

disregarding additional data in the streams of data presented to the analog circuitry during a known guard time for the data being communicated to the communication arrangement and during a second shorter data-communication interval while processing the stored data with the digital signal processing circuitry.

18. In a communication arrangement having analog circuitry and digital signal processing circuitry, the analog circuitry coupled to receive streams of data presented thereto in the form of high-frequency signals for subsequent processing by the digital signal processing circuitry, a method for reducing noise passed from the digital signal processing circuitry to the data, comprising the steps of:

using the analog circuitry to capture, process and to store the data during a first data-communication interval while the digital signal processing circuitry is in a reduced activity mode; and

disregarding additional data in the streams of data presented to the analog circuitry during a known guard time for the data being communicated to the communication arrangement and during a second shorter data-communication interval while processing the stored data with the digital signal processing circuitry.

19. A communication arrangement susceptible to processing corrupted data due to noise coupled thereto by high-speed data processing, comprising:

a chip including both digital signal processing circuitry and analog circuitry, the digital signal processing circuitry having a reduced activity mode and a high-speed data processing mode, and the analog circuitry configured and arranged to process data during a first data-communication interval while the digital signal processing circuitry is in the reduced activity mode; and

means for effectively disabling the processing of data by the analog circuitry during a known guard time for the data being communicated to the communication arrangement and during a second shorter data-communication interval while processing the data with the digital signal processing circuitry.

20. A communication arrangement, according to claim 19, wherein the analog circuitry processes data while the digital signal processing circuitry is in the reduced activity mode for at least ninety percent of a time period, and the digital signal processing circuitry processes the data for no more than the remaining portion of the time period.

21. A radio communication arrangement in which data is received using assigned frames with guard periods defined between the frames, the radio communication arrangement being susceptible to processing corrupted data due to noise coupled thereto by high-speed data processing, comprising:

a circuit including both digital signal processing circuitry and analog circuitry, the digital signal processing circuitry having a reduced activity mode and a high-speed data processing mode, and the analog circuitry configured and arranged to process data while the digital signal processing circuitry is in the reduced activity mode; and

a timer controller for causing, during the guard period, the processing of data by the analog circuitry to be effectively disabled and the digital signal processing circuitry to process the data.

22. A radio communication arrangement, according to claim 21, wherein the reduced activity mode includes at least one of:

removed power to the digital signal processing circuitry;

removed power to selected circuits forming part of the digital signal processing circuitry; and

reduced clock speeds driving various circuits that form part of the digital signal processing circuitry.