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Method and apparatus for fast automated failure classification for semiconductor wafers

  • US 6,963,813 B1
  • Filed: 09/13/2000
  • Issued: 11/08/2005
  • Est. Priority Date: 09/13/2000
  • Status: Expired due to Fees
First Claim
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1. A method for classifying patterns of failcodes on a semiconductor wafer, comprising the steps of:

  • determining failcodes for chips on the wafer;

    checking adjacent chips for each chip on the wafer having a failcode to determine a failcode pattern having a defined number of chips, wherein the step of checking comprises determining once for each chip having a failcode, adjacent chips having the same failcode, tracking adjacent chips having the same failcode, and determining a pattern of chips having the same failcode upon tracking a defined number of adjacent chips having the same failcode; and

    outputting the failcode pattern to analyze the wafer.

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