Cache device controlling a state of a corresponding cache memory according to a predetermined protocol

• US 6,963,953 B2
• Filed: 08/08/2002
• Issued: 11/08/2005
• Est. Priority Date: 12/10/2001
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Nakajima, Masami
• Primary Examiner(s): PORTKA, GARY J
• Application Number:
  US10/214,230
• Publication Number:
  US 20030110360A1
• Time in Patent Office: 1,188 Days
• Field of Search: 711/121, 711/124, 711/129, 711/130, 711/141, 711/142, 711/143, 711/144, 711/145, 711/146, 711/153, 711/173
• US Class Current: 711/129
• CPC Class Codes: G06F 12/0284 Multiple user address space allocation, e.g. using different base addresses interprocessor communication G06F15/163
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means

Abstract

It assumes that “SO” represents a state, in which that data in a responsible region storing the data to be accessed most frequently by the corresponding processor is updated in a cache memory to be controlled by a cache device, and other data is stored in other cache memory. In this case, one or more cache devices controlling each of the remaining cache memories changes the state of the data in a region other than the responsible region of the cache memory controlled by itself from “SN” to “I” (invalid). Therefore, in the case where the data designated by the same address is shared by the plurality of cache memories, the data can be invalidated in the cache memories other than the cache memory corresponding to the processor including the designated address in its own responsible region. Therefore, a data sharing rate can be low.

Claims

1. A cache device comprising at least first and second cache controllers each for controlling respective first and second cache memories, said first and second cache memories each provided to respective first and second processors sharing a shared memory with each other, said first and second cache controllers each connected to the shared memory via a bus, said first and second cache memories each comprising a plurality of data regions for temporarily storing information including data read from said shared memory by designating an address and said address designated, wherein

said shared memory includes a first space to which at least one predetermined address space of said first processor is pre-assigned and which is for storing data to be accessed most frequently by said first processor, and a second space to which at least one predetermined address space of said second processor is pre-assigned and which is for storing data to be accessed most frequently by said second processor;

said first and second cache controllers perform mutual input and output via said bus;

when said first cache controller detects that data designated by an address belonging to said predetermined address space of said first processor in said first cache memory is updated, said first cache controller outputs an invalidation request including said address for designating data corresponding to said updated data to said second cache controller via said bus if said data corresponding to said updated data is stored in said second cache memory; and

when said second cache controller receives said invalidation request from said first cache controller via said bus, said second cache controller invalidates said data corresponding to said updated data in said second cache memory based on said address in said received invalidation request.

2. The cache device according to claim 1, wherein

when said second cache controller detects that said second processor updated data designated by an address belonging to said predetermined address space of said first processor in said second cache memory, said second cache controller outputs an update request including said updated data and said address via said bus;

and

when said first cache controller receives said update request, said first cache controller updates the data corresponding to said updated data based on said address in said received update request if it is detected that said address of said received update request belongs to said predetermined address space of said first processor.

3. The cache device according to claim 1, wherein

when a plurality of predetermined address spaces corresponding to said first processor are assigned to said first space and a plurality of predetermined address spaces corresponding to said second processor are assigned to said second space, said plurality of predetermined address spaces corresponding to said first processor and said plurality of predetermine address spaces corresponding to said second processor are continuous in said shared memory, respectively.

4. The cache device according to claim 1, wherein

said first and second spaces are assigned in said shared memory in accordance with a predetermined rule.

5. The cache device according to claim 1, wherein

data in said shared memory is updated in response to every updating of data in one of said first and second cache memories.

6. The cache device according to claim 1, wherein

when said first processor refers to data in the first cache memory designated by an address belonging to said predetermined address space of said second processor, and contents in the data region corresponding to said referred data are invalid, the first cache controller outputs a copy request including the address for designating said referred data;

when said second cache controller receives said copy request via said bus and detects that said address of said received copy request corresponds to said predetermined address space of said second processor, the second cache controller reads out contents in the data region of said second cache memory storing said address of said received copy request and outputs results of the reading via said bus to said first cache controller outputting said copy request.

7. The cache device according to claim 6, wherein

when said results of reading indicate that said read contents are invalid, each of the first cache controller outputting said copy request and the second cache controller receiving said copy request reads out said data designated by the address of said copy request from said shared memory, and stores said read data in respective said first and second cache memories.

8. The cache device according to claim 1, wherein

said first and second cache controllers refer to a register provided corresponding to each of said first and second spaces in said shared memory, and

said register stores processor assignment information for representing the predetermined address space of said first processor corresponding to said first space and the predetermined address space of said second processor corresponding to said second space.

9. The cache device according to claim 8, wherein

said first and second cache controllers determine, based on results of reference to said register, whether said address belongs to said predetermined address space of said first and second processors, respectively.

10. The cache device according to claim 8, wherein

said register is provided corresponding to each page of said shared memory, and

each of said first and second spaces corresponds to each page of said shared memory.

11. The cache device according to claim 8, wherein

contents of said register are arbitrarily and variably determined.

12. The cache device according to claim 11, wherein

contents of said register are set by program processing in said first and second processors.

13. The cache device according to claim 11, wherein

contents of said register are, set based on contents of a result of counting of access to said predetermined address space corresponding said register for each of said first and second processors.

14. A cache device comprising at least first and second cache controllers each for controlling respective first and second cache memories, said first and second cache memories each provided to respective first and second processors sharing a shared memory with each other, said first and second cache controllers each connected to the shared memory via a bus, said first and second cache memories each comprising a plurality of data regions for temporarily storing information including data read from said shared memory by designating an address and said address designated, wherein

said shared memory includes a first space to which at least one predetermined address space of said first processor is pre-assigned and which is for storing data to be accessed most frequently by said first processor, and a second space to which at least one predetermined address space of said second processor is pre-assigned and which is for storing data to be accessed most frequently by said second processor;

said first and second cache controllers perform mutual input and output via said bus, said first cache controller has a first dedicated access portion for accessing one or more among said plurality of data regions of said first cache memory storing an address belonging to said predetermined address space for said first processor corresponding to said first cache memory and a first non-dedicated access portion for accessing one or more of the remaining data regions, and said second cache controller has a second dedicated access portion for accessing one or more among said plurality of data regions of said second cache memory storing an address belonging to said predetermined address space for said second processor corresponding to said second cache memory and a second non-dedicated access portion for accessing one or more of the remaining data regions;

when said first cache controller detects that data designated by an address belonging to the predetermined address space of said first processor provided with said first cache memory is updated, said first dedicated access portion of said first cache controller outputs an invalidation request including said address for designating data corresponding to said updated data to said second cache controller via said bus if said data corresponding to said updated data is stored in said second cache memory, and

when said second non-dedicated access portion of said second cache controller receives said invalidation request from said first cache controller via said bus, said second non-dedicated access portion invalidates said data corresponding to said updated data in said second cache memory based on said address in said invalidation request received.

15. The cache device according to claim 14, wherein

when said second cache controller detects that said second processor has updated data of said remaining data region of said second cache memory, said second non-dedicated access portion outputs an update request including the updated data and an address of said updated data via said bus;

and

when said first cache controller receives said update request, said first dedicated access portion updates the data corresponding to said updated data based on said address in said update request if it is detected that said address of said received update request belongs to the predetermined address space of said first processor.