Cryptographic accelerator

• US 6,963,979 B2
• Filed: 04/11/2002
• Issued: 11/08/2005
• Est. Priority Date: 10/20/1999
• Status: Expired due to Fees

• Current Assignee: AEP Systems Ltd. (AEP Networks Ltd.)
• Original Assignee: AEP Systems Ltd. (AEP Networks Ltd.)
• Inventors: Flanagan, Francis, Fairclough, Christopher
• Primary Examiner(s): Barrón, Jr., Gilberto
• Assistant Examiner(s): Lemma, Samson B.
• Application Number:
  US10/119,851
• Publication Number:
  US 20020164019A1
• Time in Patent Office: 1,307 Days
• Field of Search: 713/189, 713/153, 713/193, 713/194, 380/30, 380/28, 380/37, 708/491, 708/492
• US Class Current: 713/189
• CPC Class Codes: G06F 7/723 Modular exponentiation G06F7/724, G06F7/727, G06F7/728 take precedence
• CPC Class Codes: G06F 7/728 using Montgomery reduction

Abstract

A cryptographic accelerator (1) has a host interface (2) for interfacing with a host sending cryptographic requests and receiving results. A CPU (3) manages the internal logical unit in an exponentiation sub-system (7) having modulator exponentiators (30). The exponentiators (30) are chained together up to a maximum of four, in a block (20). There are ten blocks (20). A scheduler uses control registers and an input buffer to perform the scheduling control.

Claims

1. A cryptographic accelerator comprising:

a host interface for interfacing with a host system to receive requests for cryptographic operations and to route responses to the host system;

a plurality of logical units including an exponentiation sub-system;

a CPU connected between the host interface and the logical units for managing operation of the logical units;

said exponentiation sub-system including,

a plurality of exponentiation groups, each group having a plurality of modular exponentiators interconnected in series that define a size of each group, each exponentiator being capable of performing a multiply operation;

an input buffer for the exponentiation groups; and

a scheduler for delivering control instructions to the input buffer to dynamically configure the exponentiators so that they are dynamically and serially chained together within the groups, each chain having a number of exponentiators up to the size of the exponentiation groups to form at least one chain in each group.

2. A cryptographic accelerator as claimed in claim 1, wherein the exponentiation subsystem comprises an ASIC.

3. A cryptographic accelerator as claimed in claim 1, wherein the exponentiation subsystem comprises means for chaining modular exponentiators within a group, wherein all chains within a group are of the same length.

4. A cryptographic accelerator as claimed in claim 1, wherein the exponentiation subsystem comprises means for executing exponentiation based on the Montgomery algorithm.

5. A cryptographic accelerator as claimed in claim 3, wherein each modular exponentiator has a size of 544 bits.

6. A cryptographic accelerator as claimed in claim 1, wherein the instructions include a status field for insertion of an error in the output buffer if a result should be discarded.

7. A cryptographic accelerator as claimed in claim 1, wherein the instructions include a control field with a group mode instruction for a chaining configuration.

8. A cryptographic accelerator as claimed in claim 7, wherein the control field instruction is associated with a particular group.

9. A cryptographic accelerator as claimed in claim 1, wherein the instructions include an exponentiator block identifier field for insertion in the output buffer of an identifier of the exponentiator which generated the result.

10. A cryptographic accelerator as claimed in claim 1, wherein the instructions include a group identifier field for insertion in the output buffer of an identifier of the group which generated the result.

11. A cryptographic accelerator as claimed in claim 1, wherein the exponentiation sub-system comprises means for accessing control registers, including a register for an instruction causing the scheduler to commence initialisation of groups with exclusion of certain error-prone groups.

12. A cryptographic accelerator as claimed in claim 11, wherein a control register stores linear feedback shift register contents.

13. A cryptographic accelerator as claimed in claim 1, wherein the scheduler and the input buffer comprises means for transferring dummy data to exponentiators in the absence of real data.

14. A cryptographic accelerator as claimed in claim 1, wherein the host interface comprises a daemon and a plurality of APIs for a host system, and said daemon comprises means for managing request queues on a per-logical unit basis.

15. A cryptographic accelerator as claimed in claim 14, wherein the CPU comprises a parser comprising means for breaking each request into commands, for automatically determining a required response data space, and for allocating said space.

16. A cryptographic accelerator as claimed in claim 15, wherein each parser is associated with a particular logical unit and comprises means for breaking the commands into strings of a desired format and size for the associated logical unit.

17. A cryptographic accelerator as claimed in claim 1, wherein the CPU comprises a plurality of micro sequencers, each comprising means for either routing parsed command strings to the destination logical unit or for performing the requested operation itself.

18. A cryptographic accelerator as claimed in claim 1, wherein the logical units comprise a block cipher unit including means for implementing bulk and/or symmetric cipher operations.

19. A cryptographic accelerator as claimed in claim 1, wherein the logical units comprise a random number generator including means for generating a random number bit stream, and for performing a statistical analysis to ensure that the bits are random.

20. A cryptographic accelerator as claimed in claim 19, wherein the CPU includes means for using the random number bit stream to generate prime numbers and for storing the prime numbers in configurable pools.

21. A cryptographic accelerator as claimed in claim 1, wherein the accelerator further comprises a bus for communication of the CPU with the logical units.

22. A cryptographic accelerator comprising:

a host interface for interfacing with a host system to receive requests for cryptographic operations and to route responses to the host system;

a plurality of logical units including an exponentiation sub-system;

a CPU connected between the host interface and the logical units for managing operation of the logical units;

said exponentiation sub-system including,

a plurality of exponentiation groups, each group having a plurality of modular exponentiators interconnected in series that define a size of each group, each exponentiator being capable of performing a multiply operation;

an input buffer for the exponentiation groups;

a scheduler for delivering control instructions to the input buffer to dynamically configure the exponentiators so that they are dynamically and serially chained together within the groups, each chain having a number of exponentiators up to the size of the exponentiation groups to form at least one chain in each group; and

said scheduler configuring all chains within a group to have a same size and transferring data to the exponentiators with a relevant exponentiator block identifier, said block identifier being returned with a respective exponentiation result.