Cryptographic accelerator
First Claim
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1. A cryptographic accelerator comprising:
- a host interface for interfacing with a host system to receive requests for cryptographic operations and to route responses to the host system;
a plurality of logical units including an exponentiation sub-system;
a CPU connected between the host interface and the logical units for managing operation of the logical units;
said exponentiation sub-system including, a plurality of exponentiation groups, each group having a plurality of modular exponentiators interconnected in series that define a size of each group, each exponentiator being capable of performing a multiply operation;
an input buffer for the exponentiation groups; and
a scheduler for delivering control instructions to the input buffer to dynamically configure the exponentiators so that they are dynamically and serially chained together within the groups, each chain having a number of exponentiators up to the size of the exponentiation groups to form at least one chain in each group.
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Abstract
A cryptographic accelerator (1) has a host interface (2) for interfacing with a host sending cryptographic requests and receiving results. A CPU (3) manages the internal logical unit in an exponentiation sub-system (7) having modulator exponentiators (30). The exponentiators (30) are chained together up to a maximum of four, in a block (20). There are ten blocks (20). A scheduler uses control registers and an input buffer to perform the scheduling control.
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Citations
22 Claims
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1. A cryptographic accelerator comprising:
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a host interface for interfacing with a host system to receive requests for cryptographic operations and to route responses to the host system;
a plurality of logical units including an exponentiation sub-system;
a CPU connected between the host interface and the logical units for managing operation of the logical units;
said exponentiation sub-system including, a plurality of exponentiation groups, each group having a plurality of modular exponentiators interconnected in series that define a size of each group, each exponentiator being capable of performing a multiply operation;
an input buffer for the exponentiation groups; and
a scheduler for delivering control instructions to the input buffer to dynamically configure the exponentiators so that they are dynamically and serially chained together within the groups, each chain having a number of exponentiators up to the size of the exponentiation groups to form at least one chain in each group. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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22. A cryptographic accelerator comprising:
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a host interface for interfacing with a host system to receive requests for cryptographic operations and to route responses to the host system;
a plurality of logical units including an exponentiation sub-system;
a CPU connected between the host interface and the logical units for managing operation of the logical units;
said exponentiation sub-system including, a plurality of exponentiation groups, each group having a plurality of modular exponentiators interconnected in series that define a size of each group, each exponentiator being capable of performing a multiply operation;
an input buffer for the exponentiation groups;
a scheduler for delivering control instructions to the input buffer to dynamically configure the exponentiators so that they are dynamically and serially chained together within the groups, each chain having a number of exponentiators up to the size of the exponentiation groups to form at least one chain in each group; and
said scheduler configuring all chains within a group to have a same size and transferring data to the exponentiators with a relevant exponentiator block identifier, said block identifier being returned with a respective exponentiation result.
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Specification