Circuitized substrates utilizing three smooth-sided conductive layers as part thereof, method of making same, and electrical assemblies and information handling systems utilizing same

• US 6,964,884 B1
• Filed: 11/19/2004
• Issued: 11/15/2005
• Est. Priority Date: 11/19/2004
• Status: Expired due to Fees

• Current Assignee: I3 ELECTRONICS, INC.
• Original Assignee: Endicott Interconnect Technologies Incorporated
• Inventors: Chan, Benson, Lauffer, John M.
• Primary Examiner(s): TSAI, H JEY
• Application Number:
  US10/991,451
• Time in Patent Office: 361 Days
• Field of Search: 438106-127, 361748-769
• US Class Current: 438/118
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H05K 2201/0355 Metal foils
• CPC Class Codes: H05K 2203/0353 Making conductive layer thin, e.g. by etching
• CPC Class Codes: H05K 3/383 by microetching
• CPC Class Codes: H05K 3/4641 having integrally laminated metal sheets or special power cores

Abstract

A circuitized substrate in which three conductive layers (e.g., electroplated copper foil) are bonded (e.g., laminated) to two dielectric layers. Each of the foil surfaces which physically bond to a respective dielectric layer are smooth (e.g., preferably by chemical processing) and may include a thin, organic layer thereon. One of the conductive layers may function as a ground or voltage (power) plane while the other two may function as signal planes with a plurality of individual signal lines as part thereof. An electrical assembly and an information handling system utilizing such a circuitized substrate are also provided, as is a method of making the substrate.

Claims

1. A method of making a circuitized substrate comprising:

providing a first electrically conductive layer with first and second opposing smooth sides;

providing second and third electrically conductive layers each having a first smooth side and a second opposing side of a roughness greater than that of said first smooth sides of said second and third electrically conductive layers;

treating said first, second and third electrically conductive layers with a chemical treatment so as to minimally increase said roughness of said first and second smooth sides of said first electrically conductive layer and said first smooth sides of said second and third electrically conductive layers;

providing first and second dielectric layers;

bonding said first and second dielectric layers to said first and second opposing smooth sides of said first electrically conductive layer, respectively, after said treating of said first electrically conductive layer with said chemical treatment;

bonding said first smooth sides of said second and third electrically conductive layers to said first and second dielectric layers, respectively, after said treating of said first smooth sides of said second and third electrically conductive layers with said chemical treatment; and

forming a circuit pattern within at least one of said second and third electrically conductive layers.

2. The method of claim 1 further including treating said second sides of said second and third electrically conductive layers having said roughness greater than that of said first smooth sides with a chemical treatment so as to reduce both said roughness of said second sides of said second and third electrically conductive layers and the thickness of said second and third electrically conductive layers.

3. The method of claim 2 wherein said treating of said second sides of said second and third electrically conductive layers having said roughness greater than that of said first smooth sides with a chemical treatment so as to reduce both said roughness of said second sides of said second and third electrically conductive layers and the thickness of said second and third electrically conductive layers is accomplished using a fluid treatment device.

4. The method of claim 1 further including providing a plurality of openings within said first electrically conductive layer prior to said bonding of said first and second dielectric layers to said first electrically conductive layer.

5. The method of claim 1 wherein said bonding said first and second dielectric layers to said first and second opposing smooth sides of said first electrically conductive layer, respectively, after said treating of said first electrically conductive layer with said chemical treatment and said bonding said first smooth sides of said second and third electrically conductive layers to said first and second dielectric layers, respectively, after said treating of said first smooth sides of said second and third electrically conductive layers with said chemical treatment are accomplished substantially simultaneously.

6. The method of claim 1 wherein said treating of said first sides with said chemical treatment comprises subjecting said first sides to a solution including acid.

7. The method of claim 6 wherein said treating said first, second and third electrically conductive layers with a chemical treatment so as to minimally increase said roughness of said first and second smooth sides of said first electrically conductive layer and said first smooth sides of said second and third electrically conductive layers includes depositing a thin organic layer on said first and second smooth sides of said first electrically conductive layer and said first smooth sides of said second and third electrically conductive layers.

8. The method of claim 7 wherein said thin organic layer remains on said first and second smooth sides of said first electrically conductive layer and said first smooth sides of said second and third electrically conductive layers when said first and second dielectric layers are bonded to said first and second electrically conductive layers and said second and third electrically conductive layers are bonded to said first and second dielectric layers, respectively.

9. The method of claim 1 wherein said bonding said first and second dielectric layers to said first and second opposing smooth sides of said first electrically conductive layer, respectively, after said treating of said first electrically conductive layer with said chemical treatment and said bonding said first smooth sides of said second and third electrically conductive layers to said first and second dielectric layers, respectively, after said treating of said first smooth sides of said second and third electrically conductive layers with said chemical treatment are accomplished using a lamination process.

10. The method of claim 1 wherein said forming of said circuit pattern within said at least one of said second and third electrically conductive layers is accomplished using a chemical treatment including exposing said at least one of said electrically conductive layers to an etchant.

11. The method of claim 1 further including adding additional dielectric and electrically conductive layers on opposite sides of said circuitized substrate having said first and second dielectric layers and said first, second and third electrically conductive layers, and forming a circuit pattern within selected ones of said additional electrically conductive layers.

12. The method of claim 10 wherein the total number of dielectric layers and electrically conductive layers within said circuitized substrate is greater than ten.