Method of fabricating vertical one-transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region
First Claim
1. A method of fabricating a one-transistor, floating-body (1T/FB) dynamic random access memory (DRAM) cell, method comprising:
- forming a shallow trench isolation (STI) region in a semiconductor substrate, wherein the STI region defines a semiconductor island region in the semiconductor substrate, and wherein the STI region extends a first depth below an upper surface of the semiconductor substrate;
forming a buried source region having a first conductivity type below the upper surface of the semiconductor substrate, the buried source region having a top interface located below the upper surface of the semiconductor substrate and above the first depth, and a bottom interface located below the first depth; and
etching a recessed region in the STI region adjacent to the semiconductor island region, wherein the recessed region extends a second depth below the upper surface of the substrate, the second depth being less than the first depth, and the top interface of the source region being located above the second depth.
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Abstract
A vertical one-transistor, floating-body DRAM cell is fabricated by forming an isolation region in a semiconductor substrate, thereby defining a semiconductor island in the substrate. A buried source region is formed in the substrate, wherein the top/bottom interfaces of the buried source region are located above/below the bottom of the isolation region, respectively. A recessed region is etched into the isolation region, thereby exposing sidewalls of the semiconductor island, which extend below the top interface of the buried source region. A gate dielectric is formed over the exposed sidewalls, and a gate electrode is formed in the recessed region, over the gate dielectric. A drain region is formed at the upper surface of the semiconductor island region, thereby forming a floating body region between the drain region and the buried source region. Dielectric spacers are formed adjacent to the gate electrode, thereby covering exposed edges of the gate dielectric.
70 Citations
13 Claims
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1. A method of fabricating a one-transistor, floating-body (1T/FB) dynamic random access memory (DRAM) cell, method comprising:
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forming a shallow trench isolation (STI) region in a semiconductor substrate, wherein the STI region defines a semiconductor island region in the semiconductor substrate, and wherein the STI region extends a first depth below an upper surface of the semiconductor substrate; forming a buried source region having a first conductivity type below the upper surface of the semiconductor substrate, the buried source region having a top interface located below the upper surface of the semiconductor substrate and above the first depth, and a bottom interface located below the first depth; and etching a recessed region in the STI region adjacent to the semiconductor island region, wherein the recessed region extends a second depth below the upper surface of the substrate, the second depth being less than the first depth, and the top interface of the source region being located above the second depth. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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Specification