Thyristor-based device having dual control ports
First Claim
1. A semiconductor device comprising:
- a switching circuit having first and second base regions coupled between first and second emitter regions;
a first control port configured and arranged to capacitively couple a first signal to at least the first base region; and
a second control port configured and arranged to capacitively couple a second signal to at least the second base region, wherein the switching circuit is adapted to switch between a blocking state and a conducting state in response to at least one of the first and second signals.
4 Assignments
0 Petitions
Accused Products
Abstract
Switching operations, such as those used in memory devices, are enhanced using a thyristor-based semiconductor device adapted to switch between a blocking state and a conducting state. According to an example embodiment of the present invention, a thyristor-based semiconductor device includes a thyristor having first and second base regions coupled between first and second emitter regions, respectively. A first control port capacitively couples a first signal to the first base region, and a second control port capacitively couples a second signal to the second base region. Each of the first and second signals have a charge that is opposite in polarity, and the opposite polarity signals effect the switching of the thyristor at a lower power, relative to the power that would be required to switch the thyristor having only one control port. In this manner, power consumption for a switching operation can be reduced, which is useful, for example, to correspond with reduced power supplied to other devices in a semiconductor device employing the thyristor.
-
Citations
38 Claims
-
1. A semiconductor device comprising:
-
a switching circuit having first and second base regions coupled between first and second emitter regions;
a first control port configured and arranged to capacitively couple a first signal to at least the first base region; and
a second control port configured and arranged to capacitively couple a second signal to at least the second base region, wherein the switching circuit is adapted to switch between a blocking state and a conducting state in response to at least one of the first and second signals. - View Dependent Claims (2, 3, 4, 5, 6)
-
-
7. A semiconductor device comprising:
-
a thyristor having first and second base regions coupled to one another and respectively to first and second emitter regions;
a first control port configured and arranged to capacitively couple a first signal to at least the first base region; and
a second control port configured and arranged to capacitively couple a second signal to at least the second base region, the first and second signals having opposite polarities, wherein the thyristor is adapted to switch between a blocking state and a conducting state in response to the first and second signals. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 36, 37, 38)
-
-
35. A thyristor-based memory cell comprising:
-
a pass device including a transistor having a well region between first and second source/drain regions and a gate forming part of a first word line; and
a thyristor device comprising;
first and second base regions coupled to one another and respectively to first and second emitter regions, the second emitter region being coupled in series to the first source/drain regions of the pass device; and
a first thyristor control port forming part of a second word line and configured and arranged to capacitively couple a first signal from the second word line to the first base region; and
a second thyristor control port forming part of a third word line and configured and arranged to capacitively couple a second signal from the third word line to the second base region, the second signal being opposite in polarity to the first signal, wherein the thyristor device is adapted to switch between a blocking state and a conducting state in response to the first and second capacitively coupled signals.
-
Specification