Structure and fabricating method with self-aligned bit line contact to word line in split gate flash

• US 6,965,144 B2
• Filed: 07/29/2004
• Issued: 11/15/2005
• Est. Priority Date: 08/20/2002
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Hsieh, Chia Ta
• Primary Examiner(s): SARKAR, ASOK K
• Application Number:
  US10/901,788
• Publication Number:
  US 20050003622A1
• Time in Patent Office: 474 Days
• Field of Search: 257314-316, 257/319, 257/321, 257/322, 257/900, 365/185.01, 438/210, 438/211, 438/257, 438/264, 438/266, 438/267, 438/304, 438593-596
• US Class Current: 257/319
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A new structure is disclosed for semiconductor devices in which contact regions are self-aligned to conductive lines. Openings to a gate oxide layer, in partially fabricated devices on a silicon substrate, have insulating sidewalls. First polysilicon lines disposed against the insulating sidewalls extend from below the top of the openings to the gate oxide layer. Oxide layers are grown over the top and exposed sides of the first polysilicon lines serving to insulate the first polysilicon lines. Polysilicon contact regions are disposed directly over and connect to silicon substrate regions through openings in the gate oxide layer and fill the available volume of the openings. Second polysilicon lines connect to the contact regions and are disposed over the oxide layers grown on the first polysilicon lines.

Claims

1. A structure for semiconductor devices in which contact regions are self aligned to conductive lines, comprising:

A silicon substrate having thereon partially fabricated devices with first openings and second openings, first polysilicon lines disposed against insulating sidewalls of said openings in said partially fabricated devices on a silicon substrate, said first polysilicon lines extending from the top of the first openings to above said silicon substrate;

oxide layers formed over the top and sides of said first polysilicon lines that are not against insulating sidewalls of said second openings and serving to insulate the first polysilicon lines;

polysilicon contact regions disposed directly over and connecting to silicon substrate regions and filling said first and second openings; and

second polysilicon lines connecting to said contact regions and disposed over said oxide layers formed on said first polysilicon lines.

2. The structure of claim 1 wherein said partially fabricated devices are split gate flash cells.

3. The structure of claim 1 wherein said insulating sidewalls are sidewalls of oxide regions.

4. The structure of claim 1 wherein said first polysilicon lines are spacers serving as word lines.

5. The structure of claim 1 wherein said oxide layers grown on said first polysilicon lines are greater than about 150 Angstroms thick.

6. The structure of claim 1 wherein said silicon substrate regions connecting to said contact regions are drain regions.

7. The stricture of claim 1 wherein said second polysilicon lines are word lines connecting to drain regions.

8. A new structure for split gate flash memories in which contact regions are self aligned to conductive lines, comprising:

a silicon region extending to the surface of a semiconductor wafer with alternating parallel columns of source and drain regions;

rows of device regions that are separated by isolation regions and are perpendicular to the source/drain columns, with polysilicon contact regions disposed over drain regions connecting the drain regions to polysilicon bit lines which run in the row direction over the device regions, and said device regions as they are situated between consecutive drain regions are, in order of occurrence;

a spacer region, a floating gate region, a source line region, a floating gate region and a spacer region;

spacer regions composed of polysilicon lines, which serve as word lines in the column direction, that have oxide layers that were grown on the sides facing contact regions and on the top facing bit lines and oxide layers separating the spacer regions from the silicon region and from the adjacent floating gate region;

floating gate regions composed of a gate oxide layer over the silicon region that separates the silicon region from a polysilicon floating gate followed by an oxide layer, giving a total height some what greater than the other device regions, and oxide spacers separate the floating gate regions from adjacent source line regions;

source line regions composed of polysilicon lines in the column direction that contact source regions at the surface of the silicon region.

9. The structure of claim 8 wherein said silicon region is p-type silicon.

10. The structure of claim 8 wherein said source and drain regions are n-type silicon regions.

11. The structure of claim 8 wherein said isolation regions are shallow trench isolation regions.

12. The structure of claim 8 wherein said polysilicon contact regions, polysilicon bit lines, polysilicon word lines, polysilicon floating gates and polysilicon source lines are P doped to achieve high conductivity.

13. The structure of claim 8 wherein the grown oxide layers on said polysilicon word lines, on the sides of facing contact regions and on the top facing bit lines, are thicker than about 150 Angstroms.