Non-volatile memory device
First Claim
1. A semiconductor device comprising:
- a substrate region;
a source region formed in the substrate region;
a drain region formed in the substrate region and separated from the source region by a channel region;
a first gate overlaying a first portion of the channel and separated therefrom via a first insulating layer; and
a second gate overlaying a second portion of the channel and separated therefrom via a second insulating layer, wherein said first portion of the channel and said second portion of the channel do not overlap, wherein said first insulating layer is an oxide layer, wherein said second insulating layer further comprises a first oxide layer formed over said channel region, a first nitride layer formed over said first oxide layer of the second insulating layer, and a second oxide layer formed over said first nitride layer, and wherein said first oxide layer of the first insulating layer is thinner than the first oxide layer of the second insulating layer wherein said first gate extends partially over the second gate.
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Accused Products
Abstract
A non-volatile memory device (hereinafter alternatively referred to device) includes a guiding gate that extends along a first portion of the device'"'"'s channel length and a control gate that extends along a second portion of the device'"'"'s channel length. The first and second portions of the channel length do not overlap. The guiding gate, which overlays the substrate above the channel region, is insulated from the semiconductor substrate in which the device is formed via an oxide layer. The control gate, which also overlays the substrate above the channel region, is insulated from the substrate via an oxide-nitride-oxide layer. The device includes a source terminal, a drain terminal, a guiding gate terminal, a control gate terminal, and a substrate terminal coupled to the semiconductor substrate in which the device is formed.
40 Citations
12 Claims
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1. A semiconductor device comprising:
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a substrate region; a source region formed in the substrate region; a drain region formed in the substrate region and separated from the source region by a channel region; a first gate overlaying a first portion of the channel and separated therefrom via a first insulating layer; and a second gate overlaying a second portion of the channel and separated therefrom via a second insulating layer, wherein said first portion of the channel and said second portion of the channel do not overlap, wherein said first insulating layer is an oxide layer, wherein said second insulating layer further comprises a first oxide layer formed over said channel region, a first nitride layer formed over said first oxide layer of the second insulating layer, and a second oxide layer formed over said first nitride layer, and wherein said first oxide layer of the first insulating layer is thinner than the first oxide layer of the second insulating layer wherein said first gate extends partially over the second gate. - View Dependent Claims (3, 4, 5, 6, 7, 12)
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2. A semiconductor device comprising:
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a substrate region; a source region formed in the substrate region; a drain region formed in the substrate region and separated from the source region by a channel region; a first gate overlaying a first portion of the channel and separated therefrom via a first insulating layer; and a second gate overlaying a second portion of the channel and separated therefrom via a second insulating layer;
wherein said first portion of the channel and said second portion of the channel do not overlap, wherein said first insulating layer is an oxide layer, wherein said second insulating layer further comprises a first oxide layer formed over said channel region, a first nitride layer formed over said first oxide layer of the second insulating layer, and a second oxide layer formed over said first nitride layer, and wherein said first oxide layer of the first insulating layer is thinner than the first oxide layer of the second insulating layer wherein said second gate extends partially over the first gate. - View Dependent Claims (8, 9, 10, 11)
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Specification