Multi-layer substrates and fabrication processes

• US 6,965,158 B2
• Filed: 06/11/2002
• Issued: 11/15/2005
• Est. Priority Date: 07/07/1994
• Status: Expired due to Fees

• Current Assignee: Tessera, Inc. (Adeia Inc.)
• Original Assignee: Tessera, Inc. (Adeia Inc.)
• Inventors: Haba, Belgacem, Smith, John W.
• Primary Examiner(s): Thai, Luan
• Application Number:
  US10/167,169
• Publication Number:
  US 20020148639A1
• Time in Patent Office: 1,253 Days
• Field of Search: 257/669, 257642-643, 257/674, 257/737, 257/774, 257/781
• US Class Current: 257/669
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/5385 Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H05K 1/0289 having a matrix lay-out, i.e. having selectively interconnectable sets of X-conductors and Y-conductors in different planes
• CPC Class Codes: H05K 2201/0397 Tab forming integral conductive tabs H05K3/4092
• CPC Class Codes: H05K 2203/1327 Moulding over PCB locally or completely applying non-metallic protective coatings for encapsulating mounted components H05K3/284
• CPC Class Codes: H05K 3/4084 by deforming at least one of the conductive layers
• CPC Class Codes: H05K 3/4092 Integral conductive tabs, i.e. conductive parts partly detached from the substrate
• CPC Class Codes: H05K 3/4614 the electrical connections between the circuit boards being made during lamination
• CPC Class Codes: H05K 3/462 characterized by laminating only or mainly similar double-sided circuit boards

Abstract

Multi-layer components such as circuit panels are fabricated by connecting conductive features such as traces one two or more superposed substrates using leads extending through an intermediate dielectric layer. The leads can be closely spaced to provide a high density vertical interconnection, and can be selectively connected to provide customization of the structure.

Claims

1. A microelectronic component comprising:

(a) first and second substrates, each such substrate including at least one dielectric layer and electrically conductive features including at least one of;

(i) one or more traces extending in one or more horizontal directions along the at least one dielectric layer; and

(ii) one or more electrically conductive potential planes extending in horizontal directions along the at least one dielectric layer;

(b) a first intermediate dielectric layer disposed between said first and second substrates;

(c) a first set of elongated, electrically conductive leads affixed to said first and second substrates, said leads extending through said first intermediate layer and electrically connected between said conductive features of said first and second substrates.

2. A component as claimed in claim 1 wherein said electrically conductive features on at least one of said substrates include traces extending in one or more horizontal directions.

3. A component as claimed in claim 2 wherein at least one of substrates includes traces extending in two mutually perpendicular horizontal directions.

4. A component as claimed in claim 2 wherein said traces on at least one of said substrates are disposed on a surface of such substrate confronting said intermediate dielectric layer.

5. A component as claimed in claim 2 wherein at least some of said leads have ends on one or more of said substrates, said ends being arranged at center-to-center distances of less than about 250 μ

m.

9. A component as claimed in claim 2 wherein at least some of said leads include pairs of conductors, the conductors of each said pair being connected in parallel with one another.

10. A component as claimed in claim 1 wherein one or more of said leads are disconnected from electrical features on one or both of said substrates.

11. A component as claimed in claim 1 wherein said leads are arranged in a substantially regular pattern over at least a portion of the horizontal extent of said first and second substrates, and wherein at least one location in said pattern has a lead missing or disconnected.

13. A component as claimed in claim 1 wherein at least some of said leads are multiconductor leads, each such multiconductor lead including two or more electrical conductors and a dielectric disposed between such conductors.

14. A component as claimed in claim 13 wherein said electrically conductive features of at least one of said substrates includes sets of plural traces extending generally parallel to one another along such substrate, at least some of said sets of plural traces being connected to said multiconductor leads so that one trace of each such set is connected to one conductor of a lead whereas another trace of each such set is connected to another conductor of the same lead.

16. A component as claimed in claim 1 wherein said intermediate dielectric layer closely surrounds and encapsulates said leads, and forms a hermetic seal with said substrates.

17. A component as claimed in claim 1 wherein said first intermediate dielectric layer is compliant and said leads are flexible.

18. A component as claimed in claim 17 wherein said first and second substrates have different coefficients of thermal expansion.

19. A component as claimed in claim 18 wherein said first substrate has a coefficient of thermal expansion of less than about 6×

10<sup>−

6</sup>/°

C.

20. A component as claimed in claim 19 wherein said second substrate has a coefficient of thermal expansion of at least about 10×

10<sup>−

6</sup>/°

C.

21. A component as claimed in claim 17 wherein at least one of said substrates is flexible.

22. A component as claimed in claim 21 wherein said first substrate is flexible and has terminals thereon on exposed on a top surface facing away from said second substrate, and wherein the terminals on said first substrate are disposed in a common plane.

23. A component as claimed in claim 1 wherein said first substrate is flexible and has terminals thereon on exposed on a top surface facing away from said second substrate.

6. A microelectronic component comprising:

(a) first and second substrates, each such substrate including at least one dielectric layer and electrically conductive features including at least one of;

(i) one or more traces extending in one or more horizontal directions along the at least one dielectric layer; and

(ii) one or more electrically conductive potential planes extending in horizontal directions along the at least one dielectric layer;

(b) a first intermediate dielectric layer disposed between said first and second substrates;

(c) a first set of elongated, electrically conductive leads extending through said first intermediate layer and electrically connected between said conductive features of said first and second substrates

wherein said electrically conductive features on at least one of said substrates include traces extending in one or more horizontal directions and

wherein said traces of said first substrate include a layer of traces nearest said intermediate layer, at least some of said traces in said nearest layer adjacent said leads extending generally in an x horizontal direction, said leads including first portions projecting from said first substrate and extending generally in said x horizontal direction and sloping in a vertical direction toward said second substrate.

7. A component as claimed in claim 6 wherein said traces of said second substrate include a layer of traces nearest said intermediate layer, at least some of said traces in said nearest layer said of said second substrate adjacent said leads extending generally in a y horizontal direction perpendicular to said x horizontal direction, said leads including second portions disposed between said first portion and said second substrate and extending generally in said y horizontal direction and sloping in a vertical direction toward said second substrate.

8. A component as claimed in claim 7 wherein said leads are generally L-shaped, with said first portion of each lead extending in said x horizontal direction forming one leg of the L-shape and said second portion of each lead extending in said y horizontal direction forming the other leg of the L-shape.

12. A microelectronic component comprising:

(a) first and second substrates, each such substrate including at least one dielectric layer and electrically conductive features including at least one of;

(i) one or more traces extending in one or more horizontal directions along the at least one dielectric layer; and

(ii) one or more electrically conductive potential planes extending in horizontal directions along the at least one dielectric layer;

(b) a first intermediate dielectric layer disposed between said first and second substrates;

(c) a first set of elongated, electrically conductive leads extending through said first intermediate layer and electrically connected between said conductive features of said first and second substrates,

wherein at least one of said first and second substrates includes a cover dielectric layer overlying the conductive features and disposed between the conductive features and the intermediate dielectric layer, said cover dielectric layer having openings therein, said leads being connected to such conductive features through said openings.

15. A microelectronic component comprising:

(a) first and second substrates, each such substrate including at least one dielectric layer and electrically conductive features including at least one of;

(i) one or more traces extending in one or more horizontal directions along the at least one dielectric layer; and

(ii) one or more electrically conductive potential planes extending in horizontal directions along the at least one dielectric layer;

(b) a first intermediate dielectric layer disposed between said first and second substrates;

(c) a first set of elongated, electrically conductive leads extending through said first intermediate layer and electrically connected between said conductive features of said first and second substrates

wherein at least some of said leads are multiconductor leads, each such multiconductor lead including two or more electrical conductors and a dielectric disposed between such conductors,

at least one of said substrates having terminals exposed on a surface thereof facing away from the other said substrate, and wherein said terminals include pairs of terminals, the terminals of each such pair being disposed adjacent to one another, at least some of said pairs of terminals being connected to said multiconductor leads so that one terminal of each such pair is connected to one conductor of a lead whereas another terminal of each such pair is connected to another conductor of the same lead.

24. A microelectronic component comprising:

(a) first and second substrates, each such substrate including at least one dielectric layer and electrically conductive features including at least one of;

(i) one or more traces extending in one or more horizontal directions along the at least one dielectric layer; and

(ii) one or more electrically conductive potential planes extending in horizontal directions along the at least one dielectric layer;

(b) a first intermediate dielectric layer disposed between said first and second substrates;

(c) a first set of elongated, electrically conductive leads extending through said first intermediate layer and electrically connected between said conductive features of said first and second substrates;

further comprising a third substrate disposed between said second substrate and said first intermediate layer, a second intermediate layer disposed between said second substrate and said third substrate, and a second set of leads extending between said third substrate and second substrate and through said second intermediate layer, at least some of said leads of said first set being connected to said leads of said second set, whereby at least some of said leads of said first set are connected to conductive features of said second substrate by said leads of said second set.

25. A component as claimed in claim 24 wherein said third substrate includes one or more dielectric layers and traces extending in one or more horizontal directions along the element.

26. A substrate for use in making a multi-layer circuit panel, said substrate including:

(a) a body having a lead-bearing surface;

(b) a plurality of leads extending along said lead-bearing surface, said leads having fixed ends attached to said body and free ends movable with respect to said body, said leads extending generally in a first horizontal direction; and

(c) a plurality of electrically-conductive traces including a nearest layer of traces disposed on or adjacent to said lead-bearing surface, at least some of the traces in said nearest layer in the vicinity of said leads extending generally in said first horizontal direction.