Top layers of metal for high performance IC's

• US 6,965,165 B2
• Filed: 03/14/2003
• Issued: 11/15/2005
• Est. Priority Date: 12/21/1998
• Status: Expired due to Term

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Mou-Shiung Lin
• Inventors: Lin, Mou-Shiung
• Primary Examiner(s): QUACH, TUAN N
• Application Number:
  US10/389,543
• Publication Number:
  US 20030170934A1
• Time in Patent Office: 977 Days
• Field of Search: 257/758, 257/759, 257/760, 257/780, 257/691, 257/692, 257/778
• US Class Current: 257/758
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/76804 by forming tapered via holes
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 2224/02 Bonding areas; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/02311 Additive methods
• CPC Class Codes: H01L 2224/02313 Subtractive methods
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05184 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05671 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/05684 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/1148 Permanent masks, i.e. masks left in the finished device, e.g. passivation layers
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5222 : Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5223 : Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5225 : Shielding layers formed together with wiring layers
• CPC Class Codes: H01L 23/5227 : Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5228 : Resistive arrangements or effects of, or between, wiring layers other resistive arrangements H01L23/647
• CPC Class Codes: H01L 23/525 : with adaptable interconnections
• CPC Class Codes: H01L 23/5283 : Cross-sectional geometry
• CPC Class Codes: H01L 23/5286 : Arrangements of power or ground buses
• CPC Class Codes: H01L 23/5329 : Insulating materials
• CPC Class Codes: H01L 23/53295 : Stacked insulating layers
• CPC Class Codes: H01L 23/60 : Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 24/02 : Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 : Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 27/0676 : comprising combinations of diodes, or capacitors or resistors
• CPC Class Codes: H01L 27/08 : including only semiconductor components of a single kind
• CPC Class Codes: H01L 28/10 : Inductors
• CPC Class Codes: H01L 28/20 : Resistors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15184 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01L 2924/351 : Thermal stress
• CPC Class Codes: Y10T 428/12542 : More than one such component
• CPC Class Codes: Y10T 428/12993 : Surface feature [e.g., rough, mirror]

Abstract

A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Claims

1. A semiconductor device structure comprising:

a semiconductor substrate comprising semiconductor devices;

an interconnecting metalization structure connected to said devices;

electrical contact points on an upper surface of said interconnecting metalization structure and connected to said interconnecting metalization structure;

a passivation layer deposited over said interconnecting metalization structure and over said electrical contact points;

an insulating layer deposited over said passivation layer said insulating layer being substantially thicker than said passivation layer;

openings through said insulating layer and through said passivation layer down to the upper surface of said electrical contact points;

metal conductors within said openings; and

an upper metalization structure connected to said metal conductors.

2. A semiconductor wafer, comprising:

a semiconductor substrate having an upper passivation layer, through which contact pads are exposed, wherein semiconductor devices are formed on said semiconductor substrate, an interconnecting metallization structure comprising lower metal lines being connected to said devices; and

an upper metallization structure over said passivation layer, connected to said contact pads, comprising upper metal lines, in one or more layers, wherein said upper metal lines are substantially wider than said lower metal lines.

3. The semiconductor wafer of claim 2, wherein said one or more layers of upper metal lines are separated by organic dielectric layers.

4. The semiconductor wafer of claim 2, wherein upper contact pads are formed in a top layer of said one or more layers of said upper metal lines.

5. The semiconductor wafer of claim 4, wherein solder bumps are formed on said upper contact pads.

6. The semiconductor wafer of claim 2, wherein said upper metallization structure is configured to provide fan-out capabilities comprising:

providing a device having a plurality of contact points thereon; and

connecting each of said plurality of contact points to a contact pad through said upper metallization structure wherein a separation between said contact nads is larger than a separation between said contact points.

7. The semiconductor wafer of claim 2, wherein said upper metallization structure is configured to provide relocation capabilities comprising:

providing a device having a plurality of contact points thereon; and

connecting each of said plurality of contact points to a contact pad through said upper metallization structure wherein said connections are in a different sequence from a sequence of said contact points.

8. The semiconductor wafer of claim 2, wherein said upper metallization structure is configured to provide reduction capabilities comprising:

providing a device having a plurality of contact points thereon; and

connecting each of said plurality of contact points to one or more of said contact pads through said upper metallization structure wherein said contact pads connected are fewer in number said plurality of contact points.

9. A semiconductor wafer, comprising:

a semiconductor substrate having an upper passivation layer, through which contact pads are exposed, wherein semiconductor devices are formed on said semiconductor substrate, an interconnecting metallization structure comprising lower metal lines being connected to said devices; and

an upper metallization structure over said passivation layer, connected to said contact pads, comprising upper metal lines, in one or more layers, wherein said upper metal lines are substantially thicker than said lower metal lines.

10. The semiconductor wafer of claim 9, wherein said one or more layers of upper metal lines are separated by organic dielectric layers.

11. The semiconductor wafer of claim 9, wherein upper contact pads are formed in a top layer of said one or more layers of said upper metal lines.

12. The semiconductor wafer of claim 11, wherein solder bumps are formed on said upper contact pads.

13. The semiconductor wafer of claim 9, wherein said upper metallization structure is configured to provide fan-out, capabilities comprising:

providing a device having a niurality of contact points thereon; and

connecting each of said plurality of contact points to a contact pad through said upper metallization structure wherein a separation between said contact cads is lamer than a separation between said contact points.

14. The semiconductor wafer of claim 13, wherein said upper metallization structure is configured to provide relocation capabilities comprising:

providing a device having a plurality of contact points thereon; and

connecting each of said plurality of contact points to a contact pad through said upper metallization structure wherein said connections are in a different sequence from a sequence of said contact points.

15. The semiconductor wafer of claim 13, wherein said upper metallization structure is configured to provide reduction capabilities comprising:

providing a device having a plurality of contact points thereon; and

connecting each of said plurality of contact points to one or more of said contact pads through said upper metallization structure wherein said contact pads connected are fewer in number said plurality of contact points.