Micro-machined semiconductor package

• US 6,965,168 B2
• Filed: 02/26/2002
• Issued: 11/15/2005
• Est. Priority Date: 02/26/2002
• Status: Expired due to Fees

• Current Assignee: CTS Corporation
• Original Assignee: CTS Corporation
• Inventors: Langhorn, Jason Barnabas
• Primary Examiner(s): Lee, Eddie
• Assistant Examiner(s): Gebremariam, Samuel A
• Application Number:
  US10/082,955
• Publication Number:
  US 20030160310A1
• Time in Patent Office: 1,358 Days
• Field of Search: 257/678, 257/737, 257/778, 438/125
• US Class Current: 257/778
• CPC Class Codes: H01L 23/15 Ceramic or glass substrates H01L23/142, H01L23/145, H01L23/147 take precedence
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]

Abstract

A hermetic multi-layered ceramic semiconductor package for micro-machined semiconductor devices. The package has a substrate with top and bottom surfaces. A micro-machined semiconductor device is located adjacent to the top surface. Vias extend through the substrate between the surfaces. The micro-machined semiconductor device is electrically connected to the vias. A rigid support is located between the micro-machined semiconductor device and the top surface to support the micro-machined semiconductor device during assembly and to space the micro-machined semiconductor device from the top surface. Solder spheres are mounted to the bottom surface and are connected to the vias.

Claims

1. A semiconductor package comprising:

a planar low temperature co-fired ceramic substrate having a first and second layer mounted adjacent each other, the first layer having a first surface and the second layer having a second surface,

a micro-machined semiconductor device located adjacent the first surface, the micro-machined semiconductor device having a plurality of first pads and an active central area;

a plurality of ball pads located on the second surface;

a plurality of second pads located on the first surface;

a plurality of vias, extending through the substrate between the first and second surfaces, the vias connected to the ball pads and to the first pads;

a reflowed solder joint located between the first and second pads for electrically connecting the substrate to the semiconductor device, the reflowed solder joint formed from a first reflowed solder paste;

a solder seal ring, located between the micro-machined semiconductor device and the first surface around an outer perimeter of the substrate for making a hermetic seal between the micro-machined semiconductor device and the substrate;

a plurality of ultrasonically deposited wire bond bumps located between the micro-machined semiconductor device and the first surface for supporting the micro-machined semiconductor device during assembly and preventing the micro-machined semiconductor device from contacting the first surface during reflow of the solder joint, the wire bond bumps further spacing the micro-machined semiconductor device from the first surface, the wire bond bumps further arranged around the active area, the wire bond bumps formed from a metal;

a plurality of solder spheres mounted to the ball pads by a second reflowed solder paste; and

wherein the substrate does not have a cavity.

2. The semiconductor package according to claim 1, wherein a plurality of circuit lines are located on the first surface, the circuit lines connected between the vias and the second pads.

3. The semiconductor package according to claim 1, wherein the wire bond bumps are formed from either gold or an alloy of gold.