Method and apparatus for receiving high speed signals with low latency

• US 6,965,262 B2
• Filed: 04/15/2002
• Issued: 11/15/2005
• Est. Priority Date: 10/19/1999
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Zerbe, Jared L.
• Primary Examiner(s): Cunningham, Terry D.
• Assistant Examiner(s): Nguyen, Hai L.
• Application Number:
  US10/123,370
• Publication Number:
  US 20020153936A1
• Time in Patent Office: 1,310 Days
• Field of Search: 327/336, 327/374, 327/51, 327/52, 327/55, 327/57, 327/65, 327/69, 327/70, 327/341, 327/424, 327/427, 327/437, 326/30, 375/316, 375/318, 375/288, 455130-132
• US Class Current: 327/336
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/106 Data output latches
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1084 Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1087 Data input latches
• CPC Class Codes: G11C 7/1096 Write circuits, e.g. I/O line write drivers
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: H03K 17/162 without feedback from the output circuit to the control circuit
• CPC Class Codes: H03K 19/00323 Delay compensation
• CPC Class Codes: H03K 19/018528 with at least one differential stage
• CPC Class Codes: H03K 2005/00065 by current control, e.g. by parallel current control transistors
• CPC Class Codes: H03K 3/356034 the input circuit having a differential configuration
• CPC Class Codes: H03K 5/131 Digitally controlled
• CPC Class Codes: H03K 5/133 using a chain of active delay devices
• CPC Class Codes: H03M 5/20 the pulses having more than three levels
• CPC Class Codes: H04L 25/0276 Arrangements for coupling common mode signals
• CPC Class Codes: H04L 25/028 : Arrangements specific to the transmitter end
• CPC Class Codes: H04L 25/0292 : Arrangements specific to the receiver end
• CPC Class Codes: H04L 25/03878 : Line equalisers; line build-out devices
• CPC Class Codes: H04L 7/0332 : with an integrator-detector

Abstract

An apparatus and method for receiving high-speed signals having a wide common-mode range with low input-to-output latency. In one embodiment, the receiver includes an integrator to accumulate charge in accordance with an input signal during an integration time interval to produce an output voltage. A sense amplifier samples and converts the output voltage of the integrator to a logic signal; and a latch stores the logic signal. In an alternate embodiment, a preamplifier conditions the input signal prior to being integrated. In another embodiment using multiple receivers, circuitry is added to the receiver to compensate for timing errors associated with the distribution of the timing signals. In yet another embodiment, the integrator is coupled to an equalization circuit that compensates for intersymbol interference. In another embodiment, another circuit compensates for accumulated voltage offset errors in the integrator.

Claims

1. A multi-phased receiver system comprising:

a set of receivers coupled to a same interface pin, each receiver configured to receive an input signal from the interface pin, the input signal comprising a stream of input symbols, each input symbol having a symbol cycle time, the set of receivers configured to be sequentially activated by a set of timing signals so as to receive respective input symbols during a sequence of symbol cycles, such that each receiver determines a logic signal representing a state of its respective input symbol during a respective symbol cycle of the sequence of symbol cycles in response to the timing signals, and the set of receivers outputs the logic signal representing the state of one of the input symbols during each symbol cycle time;

wherein

the receivers are integrating receivers;

the set of timing signals include a start integration timing event, an end integration timing event and a sensing timing event for each integrating receiver, and

each integrating receiver includes;

an integrator configured to accumulate charge to produce an output voltage in accordance with the input signal during an integration time interval defined by its respective start integration timing event and end integration timing event; and

a sense amplifier configured to sample and convert the output voltage from the integrator into the logic signal in response to its respective sensing timing event substantially concurrent with the respective end integration timing event.

2. The multi-phased receiver system of claim 1 wherein the integrator of at least one of the integrating receivers is configured to accumulate the output voltage on integration nodes, the integrator further comprising:

a voltage offset cancellation circuit coupled to the integration nodes and configured to alter a precharge voltage at the integration nodes.

3. The multi-phased receiver system of claim 1 wherein the integrator of at least one of the integrating receivers is configured to operate synchronously with respect to a system clock having a first edge and a second edge, and the integrator further comprises:

a timing adjustment circuit configured to delay the start integration timing event with respect to the first edge of the system clock, wherein the sensing timing event is synchronous with the second edge of the system clock.

4. The multi-phased receiver system of claim 1, wherein each respective start integration timing event and end integration timing event for each receiver are based on a system clock having a system clock period, and a time between the start integration timing event and the end integration timing event is less than or equal to one-half of the system clock period, and each integrating receiver further comprises:

a latch to store the logic signal from the sense amplifier in response to the sensing timing event, such that an output interval defined by the sensing timing event and a time when the latch outputs the stored logic signal is less than one half-cycle of the system clock period.

5. The multi-phased receiver system of claim 4, wherein each integrating receiver further comprises:

a preamplifier configured to receive an unconditioned input signal and to provide the input signal by conditioning the unconditioned input signal.

6. The multi-phased receiver system of claim 1 wherein the integrator of each integrating receiver comprises:

a plurality of current steering blocks; and

a plurality of capacitive elements coupled to the current steering blocks, each capacitive element having integration nodes to accumulate charge, wherein at least one of the current steering blocks is configured to adjust, during the integration time interval, a charge on at least one integration node in accordance with the input signal to generate the output voltage.

7. The multi-phased receiver system of claim 1 wherein the integrator of each integrating receiver comprises:

a first current steering block;

a second current steering block; and

first and second capacitive elements, having integration nodes, coupled between the first and the second current steering blocks, wherein the first and the second current steering blocks are confimired to adjust, during the integration time interval, a charge on at least one integration node in accordance with the input signal to generate the output voltage.

8. The multi-phased receiver system of claim 7 further comprising:

a first current source, coupled to the first current steering block, to provide a first current; and

a second current source, coupled to the second current steering block, to provide a second current,

wherein the first and the second current steering blocks are configured to adjust, during the integration time interval, the charge across the capacitive elements in accordance with the first current and the second current.

9. The multi-phased receiver system of claim 8 wherein the first current is substantially the same as the second current.

10. The multi-phased receiver system of claim 7 wherein the input signal is a differential signal, the first current steering block is implemented using PMOS transistors and the second current steering block is implemented using NMOS transistors.

11. The multi-phased receiver system of claim 1 wherein a first edge of a clock signal defines the start integration timing event and a second edge of the clock signal defines the end integration timing event, wherein the sense amplifier is activated by the second clock signal edge to sample and convert the output voltage from the integrator into the logic signal.

12. The multi-phased receiver system of claim 1, wherein the start integration timing event and the end integration timing event are synchronized to a system clock having a system clock period, and a time between the start integration timing event and the end integration timing event is less than or equal to one-half of the system clock period.

13. The multi-phased receiver system of claim 1, wherein the start integration timing event and the end integration timing event are synchronized to a system clock having a system clock period, each integrating receiver further comprising:

a latch configured to store the logic signal from the sense amplifier, wherein an output interval defined by the sensing timing event to a time when the latch outputs the stored logic signal is less than or equal to one half-cycle of the system clock period.

14. The multi-phased receiver system of claim 13 wherein a time from the start integration timing event to when the latch outputs the stored logic signal is less than the system clock period.

15. The multi-phased receiver system of claim 1 wherein the integrator of each integrating receiver is configured to integrate a predetermined amount of current in accordance with a polarity of the input signal to produce the output voltage.

16. The multi-phased receiver system of claim 1 whereiz the input signal is a differential signal and the integrator of each integrating receiver is configured to integrate a predetermined amount of current in accordance with a polarity of the voltage difference of the differential input signal to produce the output voltage.

17. The multi-phased receiver system of claim 1 wherein the integrator of each integrating receiver is configured to integrate a predetermined amount of current in accordance with a polarity of the input signal with respect to a reference voltage to produce the output voltage.

18. The multi-phased receiver system of claim 1 wherein at least one of the integrating receivers further comprises:

a preamplifier configured to receive an unconditioned input signal and to condition the unconditioned input signal to generate the input signal.

19. The multi-phased receiver system of claim 1, wherein at least one of the integrating receivers further comprises:

a preamplifier configured to receive an unconditioned input signal and to condition the unconditioned input signal to provide the input signal to the integrator, wherein the input signal includes two pairs of differential conditioned signals,

wherein the integrator is configured to accumulate the charge in accordance with the polarity of the two pairs of differential conditioned signals, wherein the output voltage includes two pairs of differential integrated signals, and

the sense amplifier is configured to determine the logic signal representing the state of the input signal in accordance with the two pairs of differential integrated signals.

20. The multi-phased receiver system of claim 1 wherein the output voltage of the integrator of at least one of the integrating receivers includes two pairs of differential integrated signals, and the sense amplifier is configured to receive the two pairs of differential integrated signals and to determine the logic signal representing the state of the input signal in accordance with the two pairs of differential integrated signals.

21. The multi-phased receiver system of claim 1 wherein the integrator of at least one of the integrating receivers is configured to accumulate the output voltage on one or more pairs of integration nodes;

and

wherein the integrator further comprises a compensation circuit configured to provide a predetermined amount of charge to at least one integration node sufficient to compensate for parasitic capacitance between the integration nodes.

22. The multi-phased receiver system of claim 1, wherein the integrator of at least one of the integrating receivers is configured to accumulate the output voltage on integration nodes, the input signal includes a first bit and a second bit, wherein the first bit is received during a first bit time, and the second bit is received during a second bit time, the second bit time after the first bit time, and wherein the integrator is configured to accumulate a first output voltage for the first bit on the integration nodes during the first bit time;

the integrator further comprising;

an equalization circuit configured to adjust an initial charge on the integration nodes based on the first output voltage prior to the second bit time to compensate for inter-symbol interference between the first bit and the second bit.

23. A memory comprising:

a memory array for storing information; and

interface circuitry for coupling the memory array to a set of pins;

the interface circuitry including;

a plurality of bus receivers configured to output a plurality of logic signals, each respective bus receiver including a set of phased receivers coupled to a same respective pin of the set of pins, each phased receiver configured to receive an input signal from the respective pin, the input signal comprising a stream of input symbols, each input symbol having a symbol cycle time, the set of phased integrating receivers configured to be sequentially activated by a set of timing signals so as to receive respective input symbols during a sequence of symbol cycles, such that each phased integrating receiver determines a logic signal representing a state of its respective input symbol during a respective symbol cycle of the sequence of symbol cycles in response to the timing signals, and the set of phased integrating receivers is configured to output the logic signal representing the state of one of the input symbols during each symbol cycle time;

wherein

the set of timing signals include a start integration timing event, an end integration timing event and a sensing timing event for each phased integrating receiver; and

each phased integrating receiver includes;

an integrator configured to accumulate charge to produce an output voltage in accordance with the input signal during an integration time interval dfined by its respective start integration timing event and end integration timing event; and

a sense amplifier configured to sample and convert the output voltage from the integrator into the logic signal in response to its respective sensing timing event substantially concurrent with the respective end integration timing event.

24. The memozy of claim 23 wherein the integrator of at least one of the integrating receivers is configured to accumulate the output voltage on integration nodes, the integrator further comprising:

a voltage offset cancellation circuit coupled to the integration nodes and configured to alter a precharge voltage at the integration nodes.

25. The memoly of claim 23 wherein the integrator of at least one of the integrating receivers is configured to operate synchronously with respect to a system clock having a first edge and a second edge, and the integrator further comprises:

a timing adjustment circuit configured to delay the start integration timing event with respect to the first edge of the system clock, and wherein the sensing timing event is synchronous with the second edge of the system clock.

26. The memory of claim 23, wherein each respective start integration timing event and end integration timing event for each phased integrating receiver is based on a system clock having a system clock period, and a time between the start integration timing event and the end integration timing event is less than or equal to one-half of the system clock period, and each phased integrating receiver further comprises:

a latch configured to store the logic signal from the sense amplifier in response to the sensing timing event, such that an output interval defined by the sensing timing event and a time when the latch outputs the stored logic signal is less than one half-cycle of the system clock period.

27. The memory of claim 26, wherein each phased integrating receiver further comprises:

a preamplifier configured to receive an unconditioned input signal and to provide the input signal by conditioning the unconditioned input signal.

28. The memory of claim 23, wherein the integrator of each phased integrating receiver comprises:

a plurality of current steering blocks; and

a plurality of capacitive elements coupled to the current steering blocks, each capacitive element having integration nodes to accumulate charge, wherein at least one of the current steering blocks is configured to adjust, during the integration time interval, a charge on at least one integration node in accordance with the input signal to generate the output voltage.

29. The memory of claim 23 wherein the integrator of each phased integrating receiver comprises:

a first current steering block;

a second current steering block; and

first and second capacitive elements, having integration nodes, coupled between the first and the second current steering blocks, the first and the second current steering blocks are configured to adjust, during the integration time interval, a charge on at least one integration node in accordance with the input signal to generate the output voltage.

30. The memory of claim 29, further comprising:

a first current source, coupled to the first current steering block, to provide a first current; and

a second current source, coupled to the second current steering block, to provide a second current,

wherein the first and the second current steering blocks are configured to adjust, during the integration time interval, the charge across the capacitive elements in accordance with the first current and the second current.

31. The memory of claim 30 wherein the first current is substantially the same as the second current.

32. The memory of claim 29 wherein the input is a differential signal, the first current steering block is implemented using PMOS transistors and the second current steering block is implemented using NMOS transistors.

33. The memoty of claim 23 wherein a first edge of a clock signal defines the start integration timing event and a second edge of the clock signal defines the end integration timing event, wherein the sense amplifier is activated by the second clock signal edge to sample and convert the output voltage from the integrator into the logic signal.

34. The memory of claim 23 wherein the start integration timing event and the end integration timing event are synchronized to a system clock having a system clock period, and a time between the start integration timing event and the end integration timing event is less than or equal to one-half of the system clock period.

35. The memory claim 23 wherein the start integration timing event and the end integration timing event are synchronized to a system clock having a system clock period, each integrating receiver further comprising:

a latch configured to store the logic signal from the sense amplifier wherein an output interval defined by the sensing timing event to a time when the latch outputs the stored logic signal is less than or equal to one half-cycle of the system clock period.

36. The memory of claim 35 wherein a time from the start integration timing event to when the latch outputs the stored logic signal is less than the system clock period.

37. The memory of claim 23 wherein the integrator of each integrating receiver is configured to integrate a predetermined amount of current in accordance with a polarity of the input signal to produce output voltage.

38. The memory of claim 23 wherein the input signal is a differential signal and the integrator of each integrating receiver is configured to integrate integrate a predetermined amount of current in accordance with a polarity of the voltage difference of the differential input signal to produce the output voltage.

39. The memory of claim 23 wherein the integrator of each integrating receiver is configured to integrate a predetermined amount of current in accordance with a polarity of the input signal with respect to a reference voltage to produce the output voltage.

40. The memory of claim 23 wherein at least one of the integrating receivers further comprises:

a preamplifier configured to receive an unconditioned input signal, and to condition the unconditioned input signal to generate the input signal.

41. The memory of claim 23 wherein at least one of the integrating receivers further comprises:

a preamplifier configured to receive an unconditioned input signal, and to condition the unconditioned input signal to provide the input signal to the integrator, wherein the input signal includes two pairs of differential conditioned signals,

wherein the integrator is configured to accumulate the charge in accordance with the polarity of the two pairs of differential conditioned signals, wherein the output voltage includes two pairs of differential integrated signals, and

the sense amplifier is configured to determine the logic signal representing the state of the input signal in accordance with the two pairs of differential integrated signals.

42. The memory of claim 23 wherein the output voltage of the integrator of at least one of the integrating receivers includes two pairs of differential integrated signals, and the sense amplifier is configured to receive the two pairs of differential integrated signals and to determine the logic signal representing the state of the input signal in accordance with the two pain of differential integrated signals.

43. The memory of claim 23 wherein the integrator of at least one of the integrating receivers is configured to accumulate the output voltage on one or more pairs of integration nodes;

and

wherein the integrator further comprises a compensation circuit configured to provide a predetermined amount of charge to at least one integration node sufficient to compensate for parasitic capacitance between the integration nodes.

44. The memory of claim 23 wherein the integrator of at least one of the integrating receivers is configured to accumulate the output voltage on integration nodes, the input signal includes a first bit and a second bit, wherein the first bit is received during a first bit time, and the second bit is received during a second bit time, the second bit time after the first bit time, and wherein the integrator is configured to accumulate a first output voltage for the first bit on the integration nodes during the first bit time;

the integrator further comprising;

an equalization circuit configured to adjust an initial charge on the integration nodes based on the first output voltage prior to the second bit time to compensate for inter-symbol interference between the first bit and the second bit.