Method and system for analog to digital conversion using digital pulse width modulation (PWM)

• US 6,965,339 B2
• Filed: 04/07/2004
• Issued: 11/15/2005
• Est. Priority Date: 04/07/2004
• Status: Active Grant

• Current Assignee: Matorola, Inc.
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Rakers, Patrick L., Midya, Pallab, Miller, Matthew R.
• Primary Examiner(s): Nguyen, John B
• Application Number:
  US10/819,644
• Publication Number:
  US 20050225467A1
• Time in Patent Office: 587 Days
• Field of Search: 341/163, 341/155, 341/156, 341/143, 341/61, 341/126
• US Class Current: 341/163
• CPC Class Codes: H03M 3/00 Conversion of analogue values to or from differential modulation

Abstract

A system and method for analog-to-digital conversion using digital pulse width modulation (PWM) is disclosed. The method and system according to the disclosed invention converts an analog input signal to a digital signal in pulse code modulated (PCM) form. The disclosed invention uses a feedback circuit to perform PWM of the analog input signal. The PWM signal is then decimated to obtain the digital signal in PCM form. The system according to the disclosed invention requires lower operating frequency and dissipates lesser power than prior art systems providing the same sampling frequency and resolution. The operation at a lower frequency is achieved by obtaining two samples from every pulse of the PWM signal; the first sample being obtained from the right duty ratio, and the second sample being obtained form the left duty ratio. Further, the disclosed invention has lesser implementation complexity and higher signal-to-noise ratio than prior art.

Claims

1. A system for performing analog-to-digital conversion of an analog input signal to a digital output signal using digital pulse width modulation, the sampling frequency of the analog-to-digital conversion being controlled by a decimation clock and the resolution of the analog-to-digital conversion being controlled by a quantization clock, the system comprising:

a. an error amplifier computing an error signal using the analog input signal, the decimation clock and a digital pulse feedback signal;

b. a converter converting the error signal into the digital pulse feedback signal; and

c. a decimator decimating the digital pulse feedback signal using the decimation clock and the quantization clock to obtain the digital output signal.

2. The system according to claim 1 wherein the error amplifier is a continuous time integrating error amplifier.

3. The system according to claim 1 wherein the converter comprises:

a. a first comparator comparing a high signal and the error signal to obtain a first comparator output;

b. a second comparator comparing the error signal and a low signal to obtain a second comparator output; and

c. a JK flip-flop generating the digital pulse feedback signal using the first comparator output, the second comparator output and the quantization clock.

4. The system according to claim 1 wherein the converter comprises:

a. a hysteretic comparator comparing the error signal and the ground voltage to obtain a hysteretic comparator output signal; and

b. a D flip-flop generating the digital pulse feedback signal using the hysteretic comparator output and the quantization clock.

5. The system according to claim 1 wherein the decimator comprises:

a. a comb filter eliminating clock harmonics from the digital pulse feedback signal to obtain a comb-filtered signal;

b. a low-pass filter attenuating the high frequency quantization noise of the comb-filtered signal to obtain a low-pass filtered signal; and

c. a down-sampler down-sampling the low-pass filtered signal at a slower rate than the quantization clock to obtain the digital output signal.

6. The system according to claim 1 wherein the decimator comprises:

a. a duty-ratio counter extracting the duty ratio of the digital pulse feedback signal to obtain a duty ratio value; and

b. a plurality of look-up tables selecting the value of the digital output signal using the duty ratio value.

7. A system for performing analog-to-digital conversion of an analog input signal to a digital output signal using digital pulse width modulation, the sampling frequency of the analog-to-digital conversion being controlled by a decimation clock and the resolution of the analog-to-digital conversion being controlled by a quantization clock, the system comprising:

a. an error amplifier computing an error signal using the analog input signal and a digital PWM feedback signal pair;

b. a Flash ADC digitizing the error signal to obtain a multi-bit digital signal;

c. a pulse generator generating the digital PWM feedback signal pair using the multi-bit digital signal, the quantization clock and the decimation clock; and

d. a decimator decimating the digital PWM feedback signal pair using the decimation clock and the quantization clock to obtain the digital output signal.

8. The system according to claim 7 wherein the error amplifier is a continuous time integrating error amplifier.

9. The system according to claim 7 wherein the decimator comprises:

a. a first duty-ratio counter extracting the duty ratio of the first signal of the digital PWM feedback signal pair to obtain a first duty ratio value;

b. a second duty-ratio counter extracting the duty ratio of the second signal of the digital PWM feedback signal pair to obtain a second duty ratio value; and

c. a plurality of look-up tables selecting the value of the digital output signal using the first duty ratio value and the second duty ratio value.

10. A method for performing analog-to-digital conversion of an analog input signal to a digital output signal using digital pulse width modulation, the sampling frequency of the analog-to-digital conversion being controlled by a decimation clock and the resolution of the analog-to-digital conversion being controlled by a quantization clock, the method comprising:

a. computing an error signal using the analog input signal, the decimation clock and a digital pulse feedback signal;

b. converting the error signal into the digital pulse feedback signal; and

c. decimating the digital pulse feedback signal using the decimation clock and the quantization clock to obtain the digital output signal.

11. The method according to claim 10 wherein converting the error signal comprises:

a. comparing a high signal and the error signal to obtain a first comparator output;

b. comparing the error signal and a low signal to obtain a second comparator output; and

c. generating the digital pulse feedback signal using the first comparator output, the second comparator output and the quantization clock.

12. The method according to claim 10 wherein converting the error signal comprises:

a. comparing the error signal and the ground voltage to obtain a hysteretic comparator output signal; and

b. generating the digital pulse feedback signal using the hysteretic comparator output and the quantization clock.

13. The method according to claim 10 wherein decimating the digital pulse feedback signal comprises:

a. eliminating the clock harmonics from the digital pulse feedback signal to obtain a comb-filtered signal;

b. attenuating the high frequency quantization noise of the comb-filtered signal to obtain a low-pass filtered signal; and

c. down-sampling the low-pass filtered signal at a slower rate than the quantization clock to obtain the digital output signal.

14. The method according to claim 10 wherein decimating the digital pulse feedback signal comprises:

a. extracting the duty ratio of the digital pulse feedback signal to obtain a duty ratio value; and

b. selecting the value of the digital output signal using the duty ratio value.

15. The method according to claim 14 wherein extracting the duty ratio comprises:

a. initializing a counter to zero before the ON period of the digital pulse feedback signal;

b. incrementing the counter at a pre-determined rate during the ON period of the digital pulse feedback signal; and

c. selecting the duty ratio value using the final count of the counter.

18. The method according to claim 10 wherein one or more steps are embodied in a computer program product.

16. A method for performing analog-to-digital conversion of an analog input signal to a digital output signal using digital pulse width modulation, the sampling frequency of the analog-to-digital conversion being controlled by a decimation clock and the resolution of the analog-to-digital conversion being controlled by the quantization clock, the method comprising:

a. computing an error signal using the analog input signal and a digital PWM feedback signal pair;

b. digitizing the error signal using Flash analog-to-digital conversion to obtain a multi-bit digital signal;

c. generating the digital PWM feedback signal pair using the multi-bit digital signal, the quantization clock and the decimation clock; and

d. decimating the digital PWM feedback signal pair using the decimation clock and the quantization clock to obtain the digital output signal.

17. The method according to claim 16 wherein decimating the digital PWM feedback signal comprises:

a. extracting the duty ratio of the first signal of the digital PWM feedback signal pair to obtain a first duty ratio value;

b. extracting the duty ratio of the second signal of the digital PWM feedback signal pair to obtain a second duty ratio value; and

c. selecting the value of the digital output signal using the first duty ratio value and the second duty ratio value.

19. The method according to claim 16 wherein one or more steps are embodied in a computer program product.