Non-volatile static random access memory
First Claim
1. A memory cell comprising:
- a first MOS transistor having a first current carrying terminal coupled to a first node, a second current carrying terminal coupled to a first bitline associated with the memory cell, and a gate terminal coupled to a first terminal of the memory cell;
a second MOS transistor having a first current carrying terminal coupled to the first node, a gate terminal coupled to a second node, and a second current carrying terminal adapted to receive a first voltage;
a first non-volatile device comprising;
a first substrate region coupled to a second terminal of the memory;
a source region formed in the first substrate region and coupled to the first node;
a drain region formed in the first substrate region and separated from the source region by a first channel region;
said drain region being coupled to a third terminal of the memory cell;
a first gate overlaying a first portion of the first channel region and separated therefrom via a first insulating layer;
said first gate coupled to a fourth terminal of the memory cell; and
a second gate overlaying a second portion of the first channel region and separated therefrom via a second insulating layer;
wherein said first portion of the first channel region and said second portion of the channel do not overlap and wherein said second gate is coupled to a fifth terminal of the memory cell, said first non-volatile device being adapted so as not to include a floating gate disposed between said first and second gates thereof;
a third MOS transistor having a first current carrying terminal coupled to the second node, a second current carrying terminal coupled to a second bitline associated with the memory cell, and a gate terminal coupled to the first terminal of the memory cell;
a fourth MOS transistor having a first current carrying terminal coupled to the second node, a gate terminal coupled to the first node, and a second current carrying terminal adapted to receive the first voltage, and second non-volatile device comprising;
a second substrate region coupled to the second terminal of the memory;
a source region formed in the second substrate region and coupled to the second node;
a drain region formed in the second substrate region and separated from the source region of the second substrate region by a second channel region;
said drain region of the second substrate region being coupled to the third terminal of the memory cell;
a first gate overlaying a first portion of the second channel region and separated therefrom via a first insulating layer and coupled to the fourth terminal of the memory cell; and
a second gate overlaying a second portion of the second channel region and separated therefrom via a second insulating layer;
wherein said first portion of the second channel region and said second portion of the second channel region do not overlap and wherein said second gate overlaying the second portion of the second channel region is coupled to the fifth terminal of the memory cell said second non-volatile device being adapted so as not to include a floating gate disposed between said first and second gates thereof.
1 Assignment
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Accused Products
Abstract
In accordance with the present invention, a memory cell includes a non-volatile device and a SRAM cell. The SRAM cell includes first and second MOS transistors. The non-volatile device is a load to the SRAM cell. The memory cell may be adapted to operate differentially if a second SRAM cell and a second non-volatile device is disposed therein. If so adapted, the SRAM cells and/or the non-volatile devices when programmed store and supply complementary data. The non-volatile devices are erased prior to being programmed. Programming of the non-volatile devices may be done via hot-electron injection or Fowler-Nordheim tunneling. When a power failure occurs, the data stored in the SRAM are loaded in the non-volatile devices. After the power is restored, the data stored in the non-volatile devices are restored in the SRAM cells. The differential reading and wring of data reduces over-erase of the non-volatile devices.
56 Citations
17 Claims
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1. A memory cell comprising:
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a first MOS transistor having a first current carrying terminal coupled to a first node, a second current carrying terminal coupled to a first bitline associated with the memory cell, and a gate terminal coupled to a first terminal of the memory cell;
a second MOS transistor having a first current carrying terminal coupled to the first node, a gate terminal coupled to a second node, and a second current carrying terminal adapted to receive a first voltage;
a first non-volatile device comprising;
a first substrate region coupled to a second terminal of the memory;
a source region formed in the first substrate region and coupled to the first node;
a drain region formed in the first substrate region and separated from the source region by a first channel region;
said drain region being coupled to a third terminal of the memory cell;
a first gate overlaying a first portion of the first channel region and separated therefrom via a first insulating layer;
said first gate coupled to a fourth terminal of the memory cell; and
a second gate overlaying a second portion of the first channel region and separated therefrom via a second insulating layer;
wherein said first portion of the first channel region and said second portion of the channel do not overlap and wherein said second gate is coupled to a fifth terminal of the memory cell, said first non-volatile device being adapted so as not to include a floating gate disposed between said first and second gates thereof;
a third MOS transistor having a first current carrying terminal coupled to the second node, a second current carrying terminal coupled to a second bitline associated with the memory cell, and a gate terminal coupled to the first terminal of the memory cell;
a fourth MOS transistor having a first current carrying terminal coupled to the second node, a gate terminal coupled to the first node, and a second current carrying terminal adapted to receive the first voltage, and second non-volatile device comprising;
a second substrate region coupled to the second terminal of the memory;
a source region formed in the second substrate region and coupled to the second node;
a drain region formed in the second substrate region and separated from the source region of the second substrate region by a second channel region;
said drain region of the second substrate region being coupled to the third terminal of the memory cell;
a first gate overlaying a first portion of the second channel region and separated therefrom via a first insulating layer and coupled to the fourth terminal of the memory cell; and
a second gate overlaying a second portion of the second channel region and separated therefrom via a second insulating layer;
wherein said first portion of the second channel region and said second portion of the second channel region do not overlap and wherein said second gate overlaying the second portion of the second channel region is coupled to the fifth terminal of the memory cell said second non-volatile device being adapted so as not to include a floating gate disposed between said first and second gates thereof. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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Specification