Memory device operable in either a high-power, full-page size mode or a low-power, reduced-page size mode

• US 6,965,540 B2
• Filed: 05/20/2004
• Issued: 11/15/2005
• Est. Priority Date: 10/26/2001
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Schaefer, Scott E., Farrell, Todd D.
• Primary Examiner(s): Phung, Anh
• Assistant Examiner(s): LE, TOAN K
• Application Number:
  US10/851,879
• Publication Number:
  US 20040213036A1
• Time in Patent Office: 544 Days
• Field of Search: 365/238.5, 365/230.02, 365/230.03, 365/230.05, 365/185
• US Class Current: 365/238.5
• CPC Class Codes: G11C 11/4087 Address decoders, e.g. bit - or word line decoders; Multiple line decoders
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2207/2254 Calibration

Abstract

A memory device includes 4 memory banks each of which includes first and second arrays of memory cells. A mode register is programmed with a bit that selects a high-power, large-page operating mode or a low-power, small-page operating mode. In the high-power mode, a row decoder is coupled to the row lines in both the first and second arrays. In the low-power mode, the row decoder is coupled to the row lines in only one of the arrays as determined by the state of an array select signal. The array select signal corresponds to the most significant bit of the column address, but it is applied to the memory device at the time the row address is applied to the memory device. Sense amplifiers coupled to the first and second arrays may also be selectively enabled when the row lines for the corresponding array are coupled to the row decoder.

Claims

1. A computer system, comprising:

a processor having a processor bus;

an input device coupled to the processor through the processor bus adapted to allow data to be entered into the computer system;

an output device coupled to the processor through the processor bus adapted to allow data to be output from the computer system;

a memory controller generating a row address having a plurality of row address bits followed by a column address having a plurality of column address bits, the memory controller generating an array select signal having either a first state or a second state; and

a memory device coupled to the memory controller, the memory device comprising;

a row decoder coupled to the memory controller to receive the row address, the row decoder generating a row activate signal at one of a plurality of output terminals corresponding to the row address;

a column decoder coupled to the memory controller to receive the column address, the column decoder generating a column activate signal at one of a plurality of output terminals corresponding to the column address; and

first and second arrays of memory cells operable to store data written to or read from the array at a location determined by the row address and the column address, each of the first and second arrays having a respective set of row lines;

a data path circuit operable to couple data signals corresponding to the data between the first and second arrays and an external data terminal;

a command signal generator operable to generate a sequence of control signals corresponding to command signals applied to an external terminal;

a mode select circuit'"'"' generating a mode select signal indicative of operation in either a first or a second mode; and

a switching circuit coupled between the row decoder and the row lines of the first and second arrays, the switching circuit being operable to couple the output terminals of the row decoder to respective row lines of the first and second arrays responsive to the mode select signal indicating operation in the first mode, the switching circuit being operable to couple the output terminals of the row decoder to respective row lines of the first array but not to the row lines of the second array responsive to the mode select signal indicating operation in the second mode and the array select signal having the first state, and the switching circuit being operable to couple the output terminals of the row decoder to respective row lines of the second array but not to the row lines of the first array responsive to the mode select signal indicating operation in the second mode and the array select signal having the second state.

2. The computer system of claim 1 wherein the memory controller is operable to generate one of the column address bits as the array select signal.

3. The computer system of claim 2 wherein the memory controller is operable to couple the column address bit that is used as the array select signal to the memory device at the same time that the row address bits are coupled to the memory device.

4. The computer system of claim 2 wherein the memory controller is operable to generate a most significant column address bit as the array select signal.

5. The computer system of claim 1 wherein the mode select circuit comprises a mode register the may be programmed by an externally applied signal to store a bit corresponding to the mode select signal.

6. The computer system of claim 5 wherein the externally applied signal comprises a bank address bit.

7. The computer system of claim 1 wherein the memory controller is operable to generate the array select signal at the time the memory controller it operable to generate the row address bits.

8. The computer system of claim 1 wherein the switching circuit is further operable to couple the rows lines of the second array to a reference voltage responsive to the mode select signal indicating operation in the second mode and the array select signal having the first state, and being operable to couple the rows lines of the first array to a reference voltage responsive to the mode select signal indicating operation in the second mode and the array select signal having the second state.

9. The computer system of claim 8 wherein the reference voltage comprises ground potential.

10. The computer system of claim 1 wherein the switching circuit comprises:

a control circuit receiving the mode select signal and the array select signal, the control circuit being operable to generate first and second control signals each having a first state responsive to the mode select signal indicating operation in the first mode, the control circuit being operable to generate the first control signal having the first state and the second control signal having a second state responsive to the mode select signal indicating operation in the second mode and the array select signal having the first state, and the control circuit being operable to generate the first control signal having the second state and the second control signal having the first state responsive to the mode select signal indicating operation in the second mode and the array select signal having the second state;

a first multiplexer having a first set of input terminals coupled to the output terminals of the row decoder, a second set of input terminals coupled to a first reference voltage, a set of output terminals coupled to respective row lines of the first array, and a control terminal coupled to receive the first control signal, the first multiplexer being operable to couple the output terminals to respective input terminals of the first set responsive to the first control signal having the first state, and being operable to couple the output terminals to respective input terminals of the second set responsive to the first control signal having the second state; and

a second multiplexer having a first set of input terminals coupled to the output terminals of the row decoder, a second set of input terminals coupled to a second reference voltage, a set of output terminals coupled to respective row lines of the second array, and a control terminal coupled to receive the second control signal, the second multiplexer being operable to couple the output terminals to respective input terminals of the first set responsive to the second control signal having the first state, and being operable to couple the output terminals to respective input terminals of the second set responsive to the second control signal having the second state.

11. The computer system of claim 10 wherein the first and second reference voltages comprise ground potential.

12. The computer system of claim 1, further comprising:

a first set of sense amplifiers coupled to respective digit lines in the first array, the sense amplifiers in the first set having an enable terminal receiving a first enable signal having first and second states, power being coupled to the sense amplifiers in the first set responsive to the first enable signal having the first state, and power being decoupled from the sense amplifiers in the first set responsive to the first enable signal having the second state;

a second set of sense amplifiers coupled to respective digit lines in the second array, the sense amplifiers in the second set having an enable terminal receiving a second enable signal having first and second states, power being coupled to the sense amplifiers in the second set responsive to the second enable signal having the first state, and power being decoupled from the sense amplifiers in the second set responsive to the second enable signal having the second state; and

a control circuit receiving the mode select signal and the array select signal, the control circuit being operable to generate first and second enable signals each having the first state responsive to the mode select signal indicating operation in the first mode, the control circuit being operable to generate the first enable signal having the first state and the second enable signal having the second state responsive to the mode select signal indicating operation in the second mode and the array select signal having the first state, and the control circuit being operable to generate the first enable signal having the second state and the second enable signal having the first state responsive to the mode select signal indicating operation in the second mode and the array select signal having the second state.

13. The computer system of claim 1 wherein the memory device comprises a dynamic random access memory.

14. The computer system of claim 1 wherein the memory device comprises a plurality of memory banks each of which includes first and second arrays and a respective switching circuit coupled to the first and second arrays of each memory bank.

15. The computer system of claim 1 wherein the memory controller is operable to generate the array select signal at the same time that the memory controller generates the row address having a plurality of row address bits.

16. The computer system of claim 1 wherein the first and second arrays of memory cells comprise dynamic random accesses memory cells.

17. In a memory device, a method of addressing an array of memory cells arranged in rows and column, the method comprising:

determining within the memory device whether the memory device is to operate in either a first mode or a second mode;

receiving a row address having a first plurality of row address bits and a column address having a second plurality of column address bits;

using the row address bits to open a row of memory cells in the memory array responsive to determining that the memory device is to operate in the first mode;

using the column address bits to select a memory cell in the open row after determining that the memory device is to operate in the first mode;

using one of the column address bits to select memory cells in either a first set of columns or a second set of columns after determining that the memory device is to operate in the second mode;

using the row address bits to open a row of memory cells in the selected memory cells after determining that the memory device is to operate in the second mode; and

using the column address bits to select a memory cell in the open row after determining that the memory device is to operate in the second mode.

18. The method of claim 17 wherein the act of using one of the column address bits to select memory cells in either a first set of columns or a second set of columns after determining that the memory device is to operate in the second mode comprises using a most significant one of the column address bits to select memory cells in either a first set of columns or a second set of columns after determining that the memory device is to operate in the second mode.

19. The method of claim 18 wherein the act of using the column address bits to select a memory cell in the open row after determining that the memory device is to operate in the second mode comprises using all but the most significant bit of the column address bits to select a memory cell in the open row after determining that the memory device is to operate in the second mode.

20. The method of claim 17 wherein the act of determining within the memory device whether the memory device is to operate in either a first mode or a second mode comprises:

programming a mode register to either a first state or a second state prior to normal operation of the memory device;

examining the mode register during normal operation of the memory device to determine the programmed state of the mode register;

determining that the memory device is to operate in the first mode if the mode register has been determined to be programmed in the first state; and

determining that the memory device is to operate in the second mode if the mode register has been determined to be programmed in the second state.

21. The method of claim 20 wherein the act of programming the mode register to either the first state or the second state comprises:

externally applying a bank address bit to the mode register; and

storing the externally applied bank address bit in the mode register.

22. The method of claim 17, further comprising:

applying power to sense amplifiers coupled to the first set of columns responsive to either determining within the memory device that the memory device is to operate in the first mode or receiving the column address bit selecting the memory cells in the first set of columns after determining that the memory device is to operate m the second mode;

applying power to sense amplifiers coupled to the second set of columns responsive to either determining within the memory device that the memory device is to operate in the first mode or receiving the column address bit selecting the memory cells in the second set of columns after determining that the memory device is to operate in the second mode;

removing power from the sense amplifiers coupled to the first set of columns responsive to receiving the column address bit selecting the memory cells in the second set of columns after determining that the memory device is to operate in the second mode; and

removing power from the sense amplifiers coupled to the second set of columns responsive to receiving the column address bit selecting the memory cells in the first set of columns after determining that the memory device is to operate in the second mode.

23. A method of coupling row and column address signals to a memory device, comprising:

in a first mode, coupling M row address signals to the memory device to select one of 2^M rows of memory cells in the memory device;

in the first mode, coupling N column address signals to the memory device to select a memory cell in one of 2^N columns of memory cells in the selected row;

in a second mode, coupling M+1 row address signals to the memory device to select one of two sets of columns of memory cells in the memory device and one of 2^M rows of memory cells in the selected set of columns; and

in the second mode, coupling N−

1 columns of memory cells to the memory device to select a memory cell in one of the 2<sup>N−

1</sup> columns of memory cells in the selected row and selected set of columns.

24. The method of claim 23 wherein the act of coupling M+1 row address signals to the memory device comprises simultaneously coupling the M+1 row address signals to the memory device.

25. A method of selecting a memory cell in an array of memory cells of a memory device, the method comprising:

in a first mode, selecting one of 2^M rows of memory cells in the memory device;

in the first mode, selecting a memory cell in one of 2^N columns of memory cells in the selected row;

in a second mode, selecting one of two sets of columns of memory cells in the memory device and one of 2^M rows of memory cells in the selected set of columns; and

in the second mode, selecting a memory cell in one of the 2<sup>N−

1</sup> columns of memory cells in the selected row and selected set of columns.

26. The method of claim 25 further comprising determining within the memory device whether the memory device is operating in the first mode or the second mode.

27. The method of claim 26 wherein the act of determining within the memory device whether the memory device is to operate in either the first mode or the second mode comprises:

programming a mode resister to either a first state or a second state prior to normal operation of the memory device;

examining the mode register during normal operation of the memory device to determine the programmed state of the mode register;

determining that the memory device is to operate in the first mode if the mode register has been determined to be programmed in the first state; and

determining that the memory device is to operate in the second mode if the mode register has been determined to be programmed in the second state.

28. The method of claim 27 wherein the act of programming the mode register to either the first state or the second state comprises:

externally applying a bank address bit to the mode register; and

storing the externally applied bank address bit in the mode register.

29. The method of claim 28, further comprising:

applying power to sense amplifiers coupled to the memory cells in the first and second sets of columns of memory cells in the first operating mode;

applying power to sense amplifiers coupled to the memory cells in the first set of columns of memory cells and removing power to sense amplifiers coupled to the memory cells in the second set of columns of memory cells if the first set of columns is selected in the second operating mode; and

applying power to sense amplifiers coupled to the memory cells in the second set of columns of memory cells and removing power to sense amplifiers coupled to the memory cells in the first set of columns of memory cells if the second set of columns is selected in the second operating mode.

30. A method of operating a memory device having an array of memory cells arranged in 2^Mrows and 2^N columns, the method comprising:

in a first operating mode, addressing the memory device as a single 2^M×

2^N array of memory cells; and

in a second operating mode, addressing the memory device as two separate 2^M×

2^N/2 arrays of memory cells.

31. The method of claim 30 wherein the act of addressing the memory device as a single 2^M×

2^N array of memory cells in the first operating mode comprises;

coupling M row address bits and N column address bits to the memory device;

using the M row address bits to open one of 2^M rows of memory cells in the array; and

using the N column address bits to select a memory cell in one of 2^N columns of memory cells in the open row.

32. The method of claim 31 wherein the act of addressing the memory device as two separate 2^M×

2^N/2 arrays of memory cells in the second operating mode comprises;

coupling M row address bits and N column address bits to the memory device;

using the one of the column address bits to select one of two separate 2^M×

2^N/2 sets of memory cells

using the M row address bits to open one of 2^M rows of memory cells in the selected set of memory cells; and

using N−

1 column address bits to select a memory cell in one of 2^N/2 columns of memory cells in the open row.