Low power passive correlators for multichannel global positioning system signal receiver

• US 6,965,631 B2
• Filed: 03/13/2001
• Issued: 11/15/2005
• Est. Priority Date: 03/13/2000
• Status: Expired due to Fees

• Current Assignee: PRI Research & Development Corp.
• Original Assignee: PRI Research & Development Corp.
• Inventors: Soheili-Najafabadi, Farshid, Mehrnia, Alireza, Shakeri, Kaveh
• Primary Examiner(s): Ha, Dac V.
• Application Number:
  US09/808,372
• Publication Number:
  US 20020012387A1
• Time in Patent Office: 1,708 Days
• Field of Search: 375/130, 375/142, 375/143, 375/150, 375/152, 375/343, 370/520, 370/325, 370/342, 370/441, 370/479, 342/378, 704/218, 704/237, 704/263
• US Class Current: 375/142
• CPC Class Codes: G01S 19/30 code related G01S19/246 takes precedence
• CPC Class Codes: G01S 19/34 Power consumption
• CPC Class Codes: H04B 1/707 using direct sequence modulation
• CPC Class Codes: H04B 1/7095 Sliding correlator type

Abstract

One embodiment of the present invention includes a circular shift register, K storage elements, and a code register. The circular shift register having N data samples circularly shifts a first data sample of the N data samples into a data position at a first clock frequency. The N data samples correspond to signal received from one of K satellites in a global positioning system (GPS). The N data samples are loaded into the circular shift register at a second clock frequency. The K storage elements store K code sequences, respectively. Each of the K code sequences has N code samples and includes a first code sample being written at a code position corresponding to the data position at a third clock frequency. The K storage elements correspond to the K satellites. The code register stores the N code samples loaded from one of the K storage elements at a fourth clock frequency. The fourth clock frequency is K times faster than the first clock frequency.

Claims

1. An apparatus comprising:

a circular shift register having N data samples to circularly shift a first data sample of the N data samples into a data position at a first clock frequency, the N data samples corresponding to signal received from one of K satellites in a global positioning system (GPS), the N data samples being loaded into the circular shift register at a second clock frequency, N and K being positive integer;

K storage elements to store K code sequences, respectively, each of the K code sequences having N code samples and including a first code sample being written at a code position corresponding to the data position at a third clock frequency, the K storage elements corresponding to the K satellites; and

a code register to store the N code samples loaded from one of the K storage elements at a fourth clock frequency, the fourth clock frequency being K times faster than the first clock frequency.

2. The apparatus of claim 1 further comprising:

a write circuit coupled to the K storage elements to write the K first code samples to the K storage elements, respectively, at the K code positions synchronously with the shifted first data sample.

3. The apparatus of claim 2 wherein the write circuit comprises:

a plurality of decoders coupled to the K storage elements to enable writing the K first code samples to the K code positions synchronously with the shifted first data sample.

4. The apparatus of claim 1 further comprising:

a correlator circuit coupled to the circular shift register and the code register to compute a correlation result from the N data samples and the N code samples.

5. The apparatus of claim 4 wherein the correlator circuit comprises:

a mapper to map the N data samples and the corresponding N code samples into a plurality of mapper outputs;

an adder to add the plurality of mapper outputs to generate a result sum; and

a subtractor to subtract a bias value from the result sum to generate the correlation result.

6. The apparatus of claim 5 wherein each of the N code samples is a pseudo random noise (PN) code being represented by a one-bit value.

7. The apparatus of claim 6 wherein each of the N data samples is a two-bit with value of one of 01, 10, and 11.

8. The apparatus of claim 7 wherein each of the mapper outputs is two-bit with value of one of 01, 10, and 11.

9. The apparatus of claim 8 wherein the bias value is 44.

10. The apparatus of claim 9 wherein the correlation result is represented by 6-bit including a sign bit.

11. The apparatus of claim 1 wherein each of the K storage elements is one of a plurality of flip-flops, a register, a row in a random access memory (RAM).

12. The apparatus of claim 1 wherein N=22 and K=12.

13. The apparatus of claim 1 wherein the first clock frequency is two times a coarse/acquisition chip rate of the GPS.

14. The apparatus of claim 1 wherein the second clock frequency is equal to the first clock frequency divided by N.

15. The apparatus of claim 1 wherein the third clock frequency is equal to the first clock frequency.

16. A method comprising:

circularly shilling a first data sample of N data samples in a circular shift register into a data position at a first clock frequency, the N data samples corresponding to signal received from one of K satellites in a global positioning system (GPS), the N data samples being loaded into the circular shift register at a second clock frequency, N and K being positive integers;

storing K code sequences in K storage elements, respectively, each of the K code sequences having N code samples and including a first code sample being written at a code position corresponding to the data position at a third clock frequency, the K storage elements corresponding to the K satellites; and

storing the N code samples loaded from one of the K storage elements in a code register at a fourth clock frequency, the fourth clock frequency being K times faster than the first clock frequency.

17. The method of claim 16 further comprising:

writing the K first code samples to the K storage elements, respectively, at the K code positions synchronously with the shifted first data sample.

18. The method of claim 17 wherein writing the K first code samples comprises:

enabling writing the K first code samples to the K coda positions synchronously with the shifted first data sample.

19. The method of claim 16 further comprising:

computing a correlation result from the N data samples and the N code samples.

20. The method of claim 19 wherein computing the correlation result comprises:

mapping the N data samples and the corresponding N code samples into a plurality of mapper outputs;

adding the plurality of mapper outputs to generate a result sum; and

subtracting a bias value from the result sum to generate the correlation result.

21. The method of claim 20 wherein each of the N code samples is a pseudo random noise (PN) code being represented by a one-bit value.

22. The method of claim 21 wherein each of the N data samples is a two-bit with value of one of 01, 10, and 11.

23. The method of claim 22 wherein each of the mapper outputs is two-bit with value of one of 01, 10, and 11.

24. The method of claim 23 wherein the bias value is 44.

25. The method of claim 24 wherein the correlation result is represented by 6-bit including a sign bit.

26. The method of claim 16 wherein each of the K storage elements is one of a plurality of flip-flops, a register, a row in a random access memory (RAM).

27. The method of claim 16 wherein N=22 and K=12.

28. The method of claim 16 wherein the first clock frequency is two times a coarse/acquisition chip rate of the GPS.

29. The method of claim 16 wherein the second clock frequency is equal to the first clock frequency divided by N.

30. The method of claim 16 wherein the third clock frequency is equal to the first clock frequency.

31. A receiver comprising:

a mixer to generate mixer output samples from a signal received from one of K satellites in a global positioning system (GPS), the mixer output samples including in-phase and quadrature components, K being a positive integer;

a pseudo-random noise (PN) code generator to generate PN code sequences; and

a de-spreader circuit coupled to the mixer and the PN code generator to de-spread the mixer output samples, the de-spreader circuit comprising;

a circular shift register having N data samples of the mixer output samples to circularly shift a first data sample of the N data samples into a data position at a first clock frequency, the N data samples corresponding to the signal, the N data samples being loaded into the circular shift register at a second clock frequency, N being a positive integer,

K storage elements to store K code sequences, respectively, from the PN code generator, each of the K code sequences having N code samples and including a first code sample being written at a code position corresponding to the data position at a third clock frequency, the K storage elements corresponding to the K satellites, and

a code register to store the N code samples loaded from one of the K storage elements at a fourth clock frequency, the fourth clock frequency being K times faster than the first clack frequency.

32. The receiver of claim 31 further comprising:

a write circuit coupled to the K storage elements to write the K first code samples to the K storage elements, respectively, at the K code positions synchronously with the shifted first data sample.

33. The receiver of claim 32 wherein the write circuit comprises:

a plurality of decoders coupled to the K storage elements to enable writing the K first code samples to the K code positions synchronously with the shifted first data sample.

34. The receiver of claim 31 further comprising:

a correlator circuit coupled to the circular shift register and the code register to compute a correlation result from the N data samples and the N code samples.

35. The receiver of claim 34 wherein the correlator circuit comprises:

a mapper to map the N data samples and the corresponding N code samples into a plurality of mapper outputs;

an adder to add the plurality of mapper outputs to generate a result sum; and

a subtractor to subtract a bias value from the result sum to generate the correlation result.

36. The receiver of claim 35 wherein each of the N code samples is a pseudo random noise (PN) code being represented by a one-bit value.

37. The receiver of claim 36 wherein each of the N data samples is a two-bit with value of one of 01, 10, and 11.

38. The receiver of claim 37 wherein each of the mapper outputs is two-bit with value of one of 01, 10, and 11.

39. The receiver of claim 38 wherein the bias value is 44.

40. The receiver of claim 39 wherein the correlation result is represented by 6-bit including a sign bit.

41. The receiver of claim 40 wherein N=22 and K=12.

42. The receiver of claim 40 wherein the first clock frequency is two times a coarse/acquisition chip rate of the GPS.

43. The receiver of claim 40 wherein the second clock frequency is equal to the first clock frequency divided by N.

44. The receiver of claim 40 wherein the third clock frequency is equal to the first clock frequency.

45. The receiver of claim 31 wherein each of the K storage elements is one of a plurality of flip-flops, a register, a row in a random access memory (RAM).