Real time emulation of coherence directories using global sparse directories

• US 6,965,972 B2
• Filed: 09/25/2002
• Issued: 11/15/2005
• Est. Priority Date: 09/25/2002
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Nanda, Ashwini, Sugavanam, Krishnan
• Primary Examiner(s): Peugh, Brian R.
• Application Number:
  US10/254,745
• Publication Number:
  US 20040059876A1
• Time in Patent Office: 1,147 Days
• Field of Search: 711118-121, 711124-126, 711/130, 711/133, 711/137, 711/141, 711/147, 711/205, 711/207, 711/221, 716 16- 17, 703/27
• US Class Current: 711/141
• CPC Class Codes: G06F 12/082 Associative directories G06F12/0822 takes precedence
• CPC Class Codes: G06F 9/45537 Provision of facilities of other operating environments, e.g. WINE I/O emulation G06F13/105

Abstract

A method and structure for an emulation system comprises of a plurality of field programmable gate arrays adapted to emulate nodes of a multi-node shared memory system, a plurality of cache directories, each connected to one of the arrays, and a plurality of global coherence directories, each connected to one of the arrays. Each of the global coherence directories maintain information on all memory lines remotely cached by each of the cache directories.

Claims

1. An emulation system comprising:

a plurality of field programmable gate arrays adapted to emulate nodes of a multi-node shared memory system;

a plurality of cache directories, each connected to one of said arrays; and

a plurality of global coherence directories each connected to one of said arrays, wherein each of said global coherence directories maintains information on all memory lines in all of said cache directories;

wherein by said global coherence directories maintaining information on all memory lines remotely cached by each of said cache directories, communication among said arrays is decreased and emulation efficiency is increased.

2. The system in claim 1, wherein emulation efficiency comprises a metric which is inversely proportional to pin utilization and area utilization of said arrays.

3. An emulation system for a network of computers comprising:

a plurality of field programmable gate arrays adapted to emulate computers in said network;

a plurality of cache directories, each connected to one of said arrays; and

a plurality of global coherence directories, each connected to one of said arrays, wherein each of said global coherence directories maintains information on all memory lines in all of said cache directories,

wherein by said global coherence directories maintaining information on all memory lines remotely cached by each of said cache directories, communication among said arrays is decreased and emulation efficiency is increased.

4. The system in claim 3, wherein emulation efficiency comprises a metric which is inversely proportional to pin utilization and area utilization of said arrays.

5. A method of designing an emulation system comprising:

designing a plurality of field programmable gate arrays to emulate nodes of a multi-node shared memory system,

connecting a separate cache directory to each of said arrays; and

connecting a separate global coherence directory to each of said arrays,

wherein each said global coherence directory maintains information on all memory lines in all cache directories wherein said designing of said arrays is performed such that all nodes of said multi-node shared memory system have a copy of coherence directories of all other nodes.

6. A method of designing an emulation system comprising:

designing a plurality of field programmable gate arrays to emulate nodes of a multi-node shared memory system;

connecting a separate cache directory to each of said arrays; and

connecting a separate global coherence directory to each of said arrays,

wherein by said global coherence directories information on all memory lines remotely cached by each said cache directories, communication among said arrays is decreased and emulation efficiency is increased.

7. The method in claim 6, wherein emulation efficiency comprises a metric which is inversely proportional to pin utilization and area utilization of said arrays.