Capturing designer intent in reticle inspection

• US 6,966,047 B1
• Filed: 05/02/2002
• Issued: 11/15/2005
• Est. Priority Date: 04/09/2002
• Status: Expired due to Term

• Current Assignee: Kla-Tencor Technologies Corporation (KLA Corporation)
• Original Assignee: Kla-Tencor Technologies Corporation (KLA Corporation)
• Inventors: Glasser, Lance A.
• Primary Examiner(s): Thompson, A. M.
• Application Number:
  US10/139,109
• Time in Patent Office: 1,293 Days
• Field of Search: 716/19, 382/144, 382/149
• US Class Current: 716/52
• CPC Class Codes: G01N 2021/95615 with stored comparision signal
• CPC Class Codes: G01N 2021/95676 Masks, reticles, shadow masks
• CPC Class Codes: G01N 21/95607 using a comparative method
• CPC Class Codes: G03F 1/84 Inspecting
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06T 2207/30148 Semiconductor; IC; Wafer
• CPC Class Codes: G06T 7/0006 using a design-rule based approach

Abstract

A method of inspecting a reticle for defining a circuit layer pattern. First, the circuit layer pattern is analyzed to obtain a circuit characterization, and then, an area of the reticle is categorized into a first region and a second region based on the circuit characterization. A test reticle image of the reticle and a baseline representation containing an expected pattern of the test reticle image are provided. The first region of the test reticle image is compared to the first region of the baseline representation by a first analysis, and the second region of the test reticle image is compared to the second region of the baseline representation by a second analysis. The first analysis differs from the second analysis and this difference is based on difference in the circuit characterization of the first and second regions.

Claims

1. A circuit design for use with electronic design automation (EDA) tools in designing integrated circuits, the circuit design being stored on a computer readable medium and containing an electronic representation of a layout pattern for at least one layer of the circuit design on an integrated circuit, the layout pattern comprising:

a first layout region having a first flag associated therewith, the first layout region corresponding to a first procedure region on a reticle or an integrated circuit; and

a second layout region having a second flag or no flag associated therewith, the second layout region corresponding to a second procedure region on the reticle or the integrated circuit;

wherein

the first flag of the first layout region is readable by an inspection or a fabrication system, and indicates that the first procedure region of the reticle or the integrated circuit has a first circuit characterization type and is thereby subject to a first inspection or fabrication procedure that is to be performed on the first procedure region on the reticle or the integrated circuit;

the second flag or absence of a flag of the second layout region is readable by the inspection or the fabrication system, and indicates that the second procedure region of the reticle or integrated circuit has a second circuit characterization type and is thereby subject to a second inspection or fabrication procedure that is to be performed on the second procedure region on the reticle or the integrated circuit;

the second inspection or fabrication procedure differs from the first inspection or fabrication procedure; and

the first circuit characterization type and the second circuit characterization type identify types of structures of the first and second layout regions,

wherein the first circuit characterization type is an active transistor, and the second circuit characterization type is a decoupling transistor.

2. A circuit design for use with electronic design automation (EDA) tools in designing integrated circuits, the circuit design being stored on a computer readable medium and containing an electronic representation of a layout pattern for at least one layer of the circuit design on an integrated circuit, the layout pattern comprising:

a first layout region having a first flag associated therewith, the first layout region corresponding to a first procedure region on a reticle or an integrated circuit; and

a second layout region having a second flag or no flag associated therewith, the second layout region corresponding to a second procedure region on the reticle or the integrated circuit;

wherein

the first flag of the first layout region is readable by an inspection or a fabrication system, and indicates that the first procedure region of the reticle or the integrated circuit has a first circuit characterization type and is thereby subject to a first inspection or fabrication procedure that is to be performed on the first procedure region on the reticle or the integrated circuit;

the second flag or absence of a flag of the second layout region is readable by the inspection or the fabrication system, and indicates that the second procedure region of the reticle or integrated circuit has a second circuit characterization type and is thereby subject to a second inspection or fabrication procedure that is to be performed on the second procedure region on the reticle or the integrated circuit;

the second inspection or fabrication procedure differs from the first inspection or fabrication procedure; and

the first circuit characterization type and the second circuit characterization type identify types of structures of the first and second layout regions,

wherein the first circuit characterization type is an active element, and the second circuit characterization type is a dummy element.

3. A method of inspecting a reticle for defining a circuit layer pattern, the method comprising:

analyzing the circuit layer pattern to obtain a circuit characterization;

categorizing an area of the reticle into a first region and a second region based on the circuit characterization;

providing a test reticle image of the reticle;

providing a baseline representation containing an expected pattern of the test reticle image;

comparing the first region of the test reticle image to the first region of the baseline representation by a first analysis; and

comparing the second region of the test reticle image to the second region of the baseline representation by a second analysis;

wherein

the first analysis differs from the second analysis and this difference is based on categorization of the first and second regions; and

the circuit characterization identifies types of structures of the first and second layout regions,

wherein the circuit characterization is a function of a transistor included in the area, and

wherein the function of the transistor is a decoupling capacitor.

4. A method of inspecting a reticle for defining a circuit layer pattern, the method comprising:

analyzing the circuit layer pattern to obtain a circuit characterization;

categorizing an area of the reticle into a first region and a second region based on the circuit characterization;

providing a test reticle image of the reticle;

providing a baseline representation containing an expected pattern of the test reticle image;

comparing the first region of the test reticle image to the first region of the baseline representation by a first analysis;

comparing the second region of the test reticle image to the second region of the baseline representation by a second analysis; and

adding a flag identifying whether the circuit layer pattern is a single via area or a multiple via area to the circuit layer pattern based on a number of via holes,

wherein the first analysis differs from the second analysis and this difference is based on the flag.

5. A method of generating a layout pattern with a flag for an integrated circuit device, comprising:

generating at least one of a schematic representation and a high level description of the integrated circuit device;

generating the layout pattern based on the at least one of the schematic representation and the high level description; and

adding the flag identifying whether the layout pattern is a single via area or a multiple via area to the layout pattern based on a number of via holes.