Buried channel CMOS imager and method of forming same
First Claim
Patent Images
1. A method of forming an imaging device, comprising the steps of:
- providing a semiconductor substrate having a doped layer of a first conductivity type;
forming a first doped region of a second conductivity type in the doped layer;
forming a second doped region of said second conductivity type in the doped layer spaced from said first doped region;
forming a third doped region of said second conductivity type in the doped layer spaced from said second doped region;
forming a buried doped region of said second conductivity type in said doped layer adjacent said first and second doped regions and adjacent said second and third doped regions, wherein said buried doped region is doped at a dopant concentration less than said first, second and third doped regions;
forming a photogate over said buried doped region adjacent said first doped region;
forming a transfer gate over said buried doped region between said second and said third doped regions;
forming a contact between said second doped region and a source follower transistor wherein the gate of said source follower transistor is formed over said buried doped region.
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Abstract
A buried channel CMOS imager having an improved signal to noise ratio is disclosed. The buried channel CMOS imager provides reduced noise by keeping collected charge away from the surface of the substrate, thereby improving charge loss to the substrate. The buried channel CMOS imager thus exhibits a better signal-to-noise ratio. Also disclosed are processes for forming the buried channel CMOS imager.
41 Citations
22 Claims
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1. A method of forming an imaging device, comprising the steps of:
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providing a semiconductor substrate having a doped layer of a first conductivity type; forming a first doped region of a second conductivity type in the doped layer; forming a second doped region of said second conductivity type in the doped layer spaced from said first doped region; forming a third doped region of said second conductivity type in the doped layer spaced from said second doped region; forming a buried doped region of said second conductivity type in said doped layer adjacent said first and second doped regions and adjacent said second and third doped regions, wherein said buried doped region is doped at a dopant concentration less than said first, second and third doped regions; forming a photogate over said buried doped region adjacent said first doped region; forming a transfer gate over said buried doped region between said second and said third doped regions; forming a contact between said second doped region and a source follower transistor wherein the gate of said source follower transistor is formed over said buried doped region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method of forming an imaging device, comprising the steps of:
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providing a semiconductor substrate having a doped layer of a first conductivity type; forming a first doped region of a second conductivity type in the doped layer; forming a second doped region of said second conductivity type in the doped layer spaced from said first doped region; forming a third doped region of said second conductivity type in the doped layer spaced from said second doped region; forming a photogate over said first doped region; forming a transfer gate over said second and said third doped regions; forming a contact between said second doped region and a source follower transistor wherein the gate of said source follower transistor is over said substrate; forming a buried doped region of said second conductivity type in said doped layer adjacent said first and second doped regions and adjacent said second and third doped regions and under said photogate, transfer gate and said source follower transistor gate, wherein said buried doped region is doped at a dopant concentration less than said first, second and third doped regions. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
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Specification
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Current AssigneeMicron Technology, Inc.
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Original AssigneeMicron Technology, Inc.
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InventorsRhodes, Howard E.
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Primary Examiner(s)Mulpuri, Savitri
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Application NumberUS10/642,612Publication NumberTime in Patent Office826 DaysField of Search438 57- 99, 438510-532, 438199-233US Class Current438/73CPC Class CodesH01L 27/14609 Pixel-elements with integra...H01L 27/14643 Photodiode arrays; MOS imagersH01L 27/14689 MOS based technologies
