Storage structure with cleaved layer

• US 6,967,149 B2
• Filed: 11/20/2003
• Issued: 11/22/2005
• Est. Priority Date: 11/20/2003
• Status: Expired due to Fees

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Van Brocklin, Andrew L., Jackson, Warren, Fricke, Peter, Meyer, Neal W., Eldredge, Kenneth James
• Primary Examiner(s): Wilczewski, Mary
• Assistant Examiner(s): Thomas, Toniae M.
• Application Number:
  US10/718,137
• Publication Number:
  US 20050112846A1
• Time in Patent Office: 733 Days
• Field of Search: 438/455, 438/458, 438/459, 438/588
• US Class Current: 438/455
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Abstract

Apparatus and method for making a multi-layered storage structure includes forming a device layer on a single-crystal wafer, cleaving the device layer from the wafer, repeating the forming and cleaving to provide a plurality of cleaved device layers, and bonding the cleaved device layers together to form the multi-layered storage structure.

Claims

1. A method of making a multi-layered storage structure, comprising:

forming a device layer on a single-crystal wafer;

cleaving the device layer from the wafer;

repeating the forming and cleaving to provide a plurality of cleaved device layers;

bonding the cleaved device layers together to form the multi-layered storage structure; and

forming a three-dimensional cross-point array memory structure using the bonded device layers.

2. The method of claim 1, wherein the forming comprises implanting devices on the wafer.

3. The method of claim 1, wherein the forming comprises forming a device layer comprising devices selected from the group consisting of diodes, transistors, antifuses, and tunnel junctions.

5. The method of claim 1, wherein the repeating comprises forming the plurality of cleaved device layers from the same single-crystal wafer.

6. The method of claim 1, wherein the bonding comprises plasma-activated bonding.

7. The method of claim 1, wherein the cleaving comprises ion-implantation induced layer splitting of the wafer.

8. The method of claim 1, wherein the cleaving comprises anodic etching and annealing of the wafer.

9. The method of claim 1, wherein the storage structure comprises memory or a processor.

4. A method of making a multi-layered storage structure, comprising:

forming a device layer on a single-crystal wafer;

cleaving the device layer from the wafer;

repeating the forming and cleaving to provide a plurality of cleaved device layers; and

bonding the cleaved device layers together to form the multi-layered storage structure, wherein the forming comprises forming a device layer comprising vertical diodes;

further wherein the storage structure is a vertical memory structure.

10. A method of making a multi-layered storage structure, comprising:

forming a first device layer on a semiconductor substrate;

cleaving, from the substrate, the first device layer and a first substrate section, the first substrate section being below the first device layer and including a first portion of the substrate;

forming a second device layer on the substrate;

cleaving, from the substrate, the second device layer and a second substrate section, the second substrate section being below the second device layer and including a second portion of the substrate; and

bonding the first and second device layers to form the multi-layered storage structure.