Method for fabricating image sensor including isolation layer having trench structure

• US 6,967,316 B2
• Filed: 07/10/2003
• Issued: 11/22/2005
• Est. Priority Date: 12/27/2002
• Status: Expired due to Fees

• Current Assignee: Intellectual Ventures II LLC (Intellectual Ventures LLC)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Lee, Won-Ho
• Primary Examiner(s): LE, QUE TAN
• Application Number:
  US10/616,721
• Publication Number:
  US 20050176167A1
• Time in Patent Office: 866 Days
• Field of Search: 250/208.1, 250/239, 250/214.R, 250/214.1, 257/291, 257/292, 257/324, 257/348, 257/440, 438/207, 438/248, 438/270
• US Class Current: 250/208.1
• CPC Class Codes: H01L 27/1463 Pixel isolation structures
• CPC Class Codes: H01L 27/14689 MOS based technologies

Abstract

The present invention relates to a method for fabricating an image sensor including a device isolation layer having a trench structure. Particularly, an implantation process is performed twice to form two channel stop ion implantation regions in the course of forming the device isolation layer so that a cross-talk phenomenon between neighboring unit pixels is reduced and a leakage current is improved.

Claims

1. A method for fabricating an image sensor including a device isolation layer having a trench structure, wherein an image sensor is integrated with a depletion mode transistor and a typical transistor, the method comprising the steps of:

forming sequentially a buffer oxide layer and a pad nitride layer on a substrate;

patterning the pad nitride layer and the buffer oxide layer formed on a first region for the depletion mode transistor and a second region for the typical transistor by performing a device isolation mask process and an etch process to form trenches in the first region and the second region;

forming a spacer at lateral sides of the trenches;

masking the second region to form a high concentration of a first channel stop ion implantation region at a bottom side of the transistor in the first region by using high energy;

removing the spacer formed at the lateral sides of the trench in the first and the second regions;

masking the second region to form a low concentration of a second channel stop ion implantation region with use of low energy so that the second channel stop ion implantation region encompasses the lateral sides and the bottom side of the trench in the first region; and

burying an insulation material into the trenches in the first region and the second region.

2. The method as recited in claim 1, wherein the first channel stop ion implantation region is formed by employing high energy of about 150 KeV to about 250 KeV and a concentration ranging from about 6.0×

10¹² cm<sup>−

3</sup> to about 1.5×

10¹³ cm<sup>−

3</sup>.

3. The method as recited in claim 1, wherein the ion implantation process for forming the second channel stop ion implantation region is performed by giving a tilt angle and a rotation.

4. The method as recited in claim 3, wherein the second channel stop ion implantation region is formed by employing low energy of about 40 KeV and a concentration of about about 6.0×

10¹² cm<sup>−

3</sup>.

5. The method as recited in claim 2, wherein the first and the second channel stop ion implantation regions are formed by using boron B₁₁.

6. The method as recited in claim 1, wherein the spacer is a tetra-ethyl-ortho-silicate (TEOS) oxide layer.