Thyristor-type memory device

• US 6,967,358 B2
• Filed: 02/12/2004
• Issued: 11/22/2005
• Est. Priority Date: 06/05/1998
• Status: Expired due to Fees

• Current Assignee: Board of Trustees of the Leland Stanford Junior University (Stanford Management Co.)
• Original Assignee: Board of Trustees of the Leland Stanford Junior University (Stanford Management Co.)
• Inventors: Nemati, Farid, Plummer, James D.
• Primary Examiner(s): Tran, Michael
• Assistant Examiner(s): Nguyen, Thinh T
• Application Number:
  US10/777,453
• Publication Number:
  US 20040159853A1
• Time in Patent Office: 649 Days
• Field of Search: 257/133, 257/135, 257/155, 257/147, 257/105, 257/115, 365/180, 365/154
• US Class Current: 257/133
• CPC Class Codes: G11C 11/39 using thyristors or the avalanche or negative resistance type, e.g. PNPN, SCR, SCS, UJT
• CPC Class Codes: H01L 27/0617 comprising components of the field-effect type H01L27/0251 takes precedence
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1027 Thyristors
• CPC Class Codes: H01L 29/41716 Cathode or anode electrodes for thyristors
• CPC Class Codes: H01L 29/42308 Gate electrodes for thyristors
• CPC Class Codes: H01L 29/74 Thyristor-type devices, e.g. having four-zone regenerative action two-terminal thyristors H01L29/87
• CPC Class Codes: H01L 29/749 with turn-on by field effect
• CPC Class Codes: H01L 29/87 Thyristor diodes, e.g. Shockley diodes, break-over diodes
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element
• CPC Class Codes: H10B 12/10 DRAM devices comprising bipolar components

Abstract

A thyristor device can be used to implement a variety of semiconductor memory circuits, including high-density memory-cell arrays and single cell circuits. In one example embodiment, the thyristor device includes doped regions of opposite polarity, and a first word line that is used to provide read and write access to the memory cell. A second word line is located adjacent to and separated by an insulative material from one of the doped regions of the thyristor device for write operations to the memory cell, for example, by enhancing the switching of the thyristor device from a high conductance state to a low conductance state and/or from the low conductance state to the high conductance. This type of memory circuit can be implemented to significantly reduce standby power consumption and access time.

Claims

1. A memory cell comprising:

a thyristor device including doped regions of opposite polarity;

a first word line providing read and write access to the memory cell; and

a second word line located adjacent to and separated by an insulative material from at least one of the doped regions of the thyristor device and used for write operation to the memory cell by enhancing the switching of the thyristor device from a high conductance state to a low conductance state and from the low conductance state to the high conductance state.

2. The memory cell of claim 1, further comprising a transistor, wherein the read and write access is provided by the transistor with its gate forming at least part of the first word line.

3. The memory cell of claim 2, wherein the transistor is a MOSFET transistor.

4. The memory cell of claim 1, wherein the second word line enhances the switching of the thyristor device by substantially improving the switching speed of the thyristor device from the high conductance state to the low conductance state.

5. The memory cell of claim 1, wherein the second word line is adapted to enhance the switching of the thyristor device by substantially reducing the voltage requirement of the thyristor device for switching from the low conductance state to the high conductance state.

6. The memory cell of claim 1, wherein at least part of the cell is arranged in a vertical configuration extending above a substrate surface.

7. The memory cell of claim 1, wherein at least part of the cell is arranged in a vertical configuration extending below a substrate surface.

8. The memory cell of claim 1, wherein at least part of the cell is arranged in a planar configuration parallel to a substrate surface.

9. The memory cell of claim 8, wherein the substrate surface is part of a silicon-on-insulator substrate.

10. The memory cell of claim 2, wherein the transistor and the thyristor device are arranged in a planar configuration parallel to a substrate surface.

11. The memory cell of claim 10, wherein the substrate surface is part of a silicon-on-insulator substrate.

12. A memory array comprising:

a first and a second word line; and

a plurality of memory cells, each memory cell comprising a thyristor device including doped regions of opposite polarity, wherein

the first word line providing read and write access to the memory cell; and

a portion of the second word line located adjacent to and separated by an insulative material from at least one of the doped regions of the thyristor device and used for write operation to the memory cell by enhancing the switching of the thyristor device from a high conductance state to a low conductance state and from the low conductance state to the high conductance state.

13. The memory array of claim 12, wherein the memory cell further comprises a transistor, and wherein the read and write access is provided by the transistor with its gate forming at least part of the first word line.

14. The memory array of claim 13, wherein the transistor is a MOSFET transistor.

15. The memory array of claim 12, wherein the second word line enhances the switching of the thyristor device by substantially improving the switching speed of the thyristor device from the high conductance state to the low conductance state.

16. The memory array of claim 12, wherein the second word line enhances the switching of the thyristor device by substantially reducing the voltage requirement of the thyristor device for switching from the low conductance state to the high conductance state.

17. The memory array of claim 12, wherein at least part of the memory cell is arranged in a vertical configuration extending above a substrate surface.

18. The memory array of claim 12, wherein at least part of the memory cell is arranged in a vertical configuration extending below a substrate surface.

19. The memory array of claim 12, wherein at least part of the memory cell is arranged in a planar configuration parallel to a substrate surface.

20. The memory array of claim 19, wherein the substrate surface is part of a silicon-on-insulator substrate.

21. The memory array of claim 13, wherein the transistor and the thyristor device are arranged in a planar configuration parallel to a substrate surface.

22. The memory array of claim 21, wherein the substrate surface is part of a silicon-on-insulator substrate.