Wafer-interposer assembly

• US 6,967,494 B2
• Filed: 02/05/2004
• Issued: 11/22/2005
• Est. Priority Date: 07/31/2000
• Status: Expired due to Fees

• Current Assignee: Transpacific Multicast, LLC
• Original Assignee: Eaglestone Partners I LLC
• Inventors: Kline, Jerry D.
• Primary Examiner(s): Karlsen, Ernest F.
• Application Number:
  US10/772,951
• Publication Number:
  US 20040155328A1
• Time in Patent Office: 656 Days
• Field of Search: 324/754, 324/755, 324/757, 324/760, 324/765, 324/158.1, 438/17, 438/18, 257/48, 257/727, 257/734, 257/773, 257/777, 257/778
• US Class Current: 324/754.18
• CPC Class Codes: B33Y 80/00 Products made by additive manufacturing
• CPC Class Codes: H01L 23/49805 the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A wafer-interposer assembly (10) includes a semiconductor wafer (12) having a plurality of semiconductor die (14) that have a plurality of first electrical contact pads (16). An interposer (22) is connected to the semiconductor wafer (12) such that a plurality of second electrical contact pads (26) associated with the interposer (22) are respectively connected to at least some of the first electrical contact pads (16) via conductive attachment elements (20). A communication interface (28) is integrally associated with the interposer (22) and electrically connected to at least some of the plurality of second electrical contact pads (26). The interposer (22) and the semiconductor wafer (12) are operable to be singulated into a plurality of chip assemblies.

Claims

1. A wafer-interposer assembly comprising:

a semiconductor wafer including a plurality of semiconductor die, each semiconductor die having a plurality of first electrical contact pads;

an interposer electrically connected and mechanically secured to the semiconductor wafer, the interposer including a plurality of second electrical contact pads respectively electrically connected and mechanically secured to at least some of the first electrical contact pads via soldered connections such that the interposer and the semiconductor wafer are operable to be singulated into a plurality of chip assemblies, each chip assembly comprising a semiconductor die and a portion of the interposer electrically connected and mechanically secured to one another via soldered connections; and

a communication interface integrally associated with the interposer and electrically connected to at least some of the second electrical contact pads.

2. The water-interposer assembly as recited in claim 1 wherein the communication interface further comprises an integral edge connector with pins.

3. The water-interposer assembly as recited in claim 1 wherein the communication interface further comprises an integral bayonet connector with pins.

4. The wafer-interposer assembly as recited in claim 1 wherein the communication interface further comprises a connector added to the wafer-interposer assembly.

5. The wafer-interposer assembly as recited in claim 1 wherein the communication interface further comprises soldered connections.

6. The wafer-interposer assembly as recited in claim 1 wherein the communication interface further comprises a ribbon connector.

7. The wafer-interposer assembly as recited in claim 1 wherein the communication interface further comprises an RF connector.

8. The wafer-interposer assembly as recited in claim 1 wherein the communication interface further comprises an optical connector.

9. The wafer-interposer assembly as recited in claim 1 wherein the communication interface further comprises a transmit/receive antenna.

10. The wafer-interposer assembly as recited in claim 1 wherein the communication interface further comprises a quick release device.

11. The wafer-interposer assembly as recited in claim 1 wherein the communication interface is operably coupled to a testing apparatus that tests at least some of the semiconductor die prior to the singulation of the interposer and the semiconductor wafer.

12. The wafer-interposer assembly as recited in claim 1 wherein the communication interface is operably coupled to a testing apparatus that burn-in tests at least some of the semiconductor die prior to the singulation of the interposer and the semiconductor wafer.

13. A wafer-interposer assembly comprising:

a semiconductor wafer including a plurality of semiconductor die having a pattern of first electrical contact pads disposed thereon;

an interposer electrically connected and mechanically secured to the semiconductor wafer, the interposer having a first surface with a pattern of second electrical contact pads disposed thereon, at least some of which correspond to and are electrically connected and mechanically secured to at least some of the first electrical contact pads via soldered connections, the interposer also having a second surface having a pattern of third electrical contact pads that are electrically connected to at least some of the second electrical contact pads, such that the interposer and the semiconductor wafer are operable to be singulated into a plurality of chip assemblies, each including a semiconductor die and a portion of the interposer that remain electrically connected and mechanically secured to one another via soldered connections; and

a communication interface integrally associated with the interposer and electrically connected to at least some of the second electrical contact pads.

14. The wafer-interposer assembly as recited in claim 13 wherein the communication interface further comprises an integral edge connector with pins.

15. The wafer-interposer assembly as recited in claim 13 wherein the communication interface further comprises an integral bayonet connector with pins.

16. The wafer-interposer assembly as recited in claim 13 wherein the communication interface further comprises a connector added to the wafer-interposer assembly.

17. The wafer-interposer assembly as recited in claim 13 wherein the communication interface further comprises soldered connections.

18. The wafer-interposer assembly as recited in claim 13 wherein the communication interface further comprises a ribbon connector.

19. The wafer-interposer assembly as recited in claim 13 wherein the communication interface further comprises an RF connector.

20. The wafer-interposer assembly as recited in claim 13 wherein the communication interface further comprises an optical connector.

21. The wafer-interposer assembly as recited in claim 13 wherein the communication interface further comprises a transmit/receive antenna.

22. The wafer-interposer assembly as recited in claim 13 wherein the communication interface further comprises a quick release device.

23. The wafer-interposer assembly as recited in claim 13 wherein the communication interface is operably coupled to a testing apparatus that tests at least some of the semiconductor die prior to the singulation of the interposer and the semiconductor wafer.

24. The water-interposer assembly as recited in claim 13 wherein the communication interface is operably coupled to a testing apparatus that burn-in tests at least some of the semiconductor die prior to the singulation of the interposer and the semiconductor wafer.