PLL having VCO for dividing frequency

• US 6,967,538 B2
• Filed: 06/25/2003
• Issued: 11/22/2005
• Est. Priority Date: 11/28/2002
• Status: Expired due to Term

• Current Assignee: Abov Semiconductor Co., Ltd.
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Woo, Sung Hun
• Primary Examiner(s): Pascal, Robert
• Assistant Examiner(s): Chang, Joseph
• Application Number:
  US10/603,647
• Publication Number:
  US 20040104780A1
• Time in Patent Office: 881 Days
• Field of Search: 331/74, 331/36.C, 331/68, 327/156, 327/147
• US Class Current: 331/73
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/104 using an additional signal from outside the loop for setting or controlling a parameter in the loop H03L7/107, H03L7/12 take precedence
• CPC Class Codes: H03L 7/187 using means for coarse tuning the voltage controlled oscillator of the loop H03L7/191 - H03L7/195 take precedence
• CPC Class Codes: H03L 7/193 the frequency divider/counter comprising a commutable pre-divider, e.g. a two modulus divider

Abstract

A PLL comprising a phase detector, a loop filter and a VCO is disclosed. The phase detector periodically compares an externally inputted clock signal with a frequency of an internal clock signal, and outputs an output signal resulting from phase difference of the two signals. The loop filter outputs a predetermined voltage in response to an output signal from said phase detector. The VCO outputs said internal clock signal having a frequency proportional to said predetermined voltage. Here, the VCO includes a capsule for adjusting the value of capacitance using an internal control signal. As a result, frequencies may be pre-compensated by control signals used in the PLL. In addition, the disclosed PLL having a VCO therein can be configured into a single chip, thereby simplifying the embodiment of the whole PLL and enabling accurate compensation.

Claims

1. A PLL comprising:

a phase detector for periodically comparing an externally inputted clock signal with a frequency of an internal clock signal, and outputting an output signal resulting from phase difference between the two signals;

a loop filter for outputting a predetermined voltage in response to an output signal from said phase detector; and

a VCO for outputting said internal clock signal having a frequency proportional to said predetermined voltage,

wherein said VCO comprises a capsule for adjusting the value of capacitance by using an internal control signal, said capsule comprising;

a plurality of first capacitors connected in parallel to an output terminal of said VCC.

2. The PLL according to claim 1, wherein said capsule comprises a plurality of first switches connected, between said output terminal and the plurality of said first capacitors, respectively, and to be controlled in response to a plurality of control signals generated by using said internal control signal.

3. The PLL according to claim 1, wherein said capsule comprises a plurality of second capacitors connected in series between output terminals of said VCO.

4. The PLL according to claim 3, wherein said capsule comprises a plurality of second switches configured to be connected between an output terminal and the plurality of said second capacitors, and to be controlled in response to a plurality of control signals generated by using said internal control signal.

5. The PLL according to claim 4, wherein the plurality of said second switches is connected in parallel between an output terminal and the plurality of said second capacitors.