Low power bit and one-half analog to digital converter

• US 6,967,610 B1
• Filed: 09/21/2004
• Issued: 11/22/2005
• Est. Priority Date: 12/06/2002
• Status: Expired due to Term

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Sutardja, Sehat, Aram, Farbod
• Primary Examiner(s): WAMSLEY, PATRICK G
• Application Number:
  US10/946,321
• Time in Patent Office: 427 Days
• Field of Search: 341/155, 341/122, 341/135, 341/142, 341/143, 341/161, 341/172, 327/337, 327/170, 327/541, 323/282, 330/2, 331/17
• US Class Current: 341/161
• CPC Class Codes: H03M 1/002 Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
• CPC Class Codes: H03M 1/0695 using less than the maximum number of output states per stage or step, e.g. 1.5 per stage or less than 1.5 bit per stage type
• CPC Class Codes: H03M 1/168 and delivering the same number of bits
• CPC Class Codes: H03M 1/442 using switched capacitors

Abstract

A bit-and-one-half analog to digital converter comprises a switched capacitor circuit, including an opamp, that receives an analog input voltage and generates a residual analog output voltage. The switched capacitor circuit samples the analog input voltage during a sampling phase and generates the residual analog output voltage during an integration phase. A comparator generates a digital output based on the analog output voltage generated by the switched capacitor circuit. A current source communicates with the opamp and is operable to supply a first bias current to the opamp during the sampling phase and a second bias current that is greater than the first bias current to the opamp during the integration phase.

Claims

1. A bit-and-one-half analog to digital converter, comprising:

a switched capacitor circuit, including an opamp, that receives an analog input voltage and generates a residual analog output voltage, wherein said switched capacitor circuit samples said analog input voltage during a sampling phase and generates said residual analog output voltage during an integration phase;

a comparator that generates a digital output based on said analog output voltage generated by said switched capacitor circuit; and

a current source that communicates with said opamp and is operable to supply a first bias current to said opamp during said sampling phase and a second bias current that is greater than said first bias current to said opamp during said integration phase.

2. The bit-and-one-half analog to digital converter of claim 1 wherein said switched capacitor circuit includes a capacitor that stores said sampled analog input voltage during said sampling phase.

3. The bit-and-one-half analog to digital converter of claim 2 wherein said sampled analog input voltage stored by said capacitor is integrated by said opamp during said integration phase to generate said residual analog output voltage.

4. The bit-and-one-half analog to digital converter of claim 1 wherein said first bias current is a fractional portion of said second bias current.

5. The bit-and-one-half analog to digital converter of claim 1 wherein said first bias current is zero.

6. A multi-stage pipelined analog to digital converter, comprising:

a plurality of bit-and-one-half converter stages arranged in series, each converter stage receiving an analog input voltage and generating a residual analog output voltage, wherein each converter stage further comprises;

a switched capacitor circuit, including an opamp, that receives said analog input voltage and generates said residual analog output voltage, wherein said switched capacitor circuit samples said analog input voltage during a sampling phase and generates said residual analog output voltage during an integration phase;

a comparator that generates a digital stage output based on said residual analog output voltage generated by said switched capacitor circuit;

a current source that communicates with said opamp and is operable to supply a first bias current to said opamp during said sampling phase and a second bias current that is greater than said first bias current to said operation amplifier during said integration phase; and

a correction circuit that accepts said digital stage output from each of said converter stages and generates a corresponding digital output.

7. The multi-stage pipelined analog to digital converter of claim 6 wherein said switched capacitor circuit includes a capacitor that stores said sampled analog input voltage during said sampling phase.

8. The multi-stage pipelined analog to digital converter of claim 7 wherein said sampled analog input voltage stored by said capacitor is integrated by said opamp during said integration phase to generate said residual analog output voltage.

9. The multi-stage pipelined analog to digital converter of claim 6 wherein said first bias current is a fractional portion of said second bias current.

10. The multi-stage pipelined analog to digital converter of claim 6 wherein said first bias current is zero.

11. A bit-and-one-half analog to digital converter, comprising:

switched capacitor means, including integrating means for integrating signals input thereto, for receiving an analog input voltage and for generating a residual analog output voltage, wherein said switched capacitor means samples said analog input voltage during a sampling phase and generates said residual analog output voltage during an integration phase;

comparing means for generating a digital output based on said analog output voltage generated by said switched capacitor means; and

current means that communicates with said integrating means for supplying a first bias current to said integrating means during said sampling phase and a second bias current that is greater than said first bias current to said integrating means during said integration phase.

12. The bit-and-one-half analog to digital converter of claim 11 wherein said switched capacitor means includes a capacitor that stores said sampled analog input voltage during said sampling phase.

13. The bit-and-one-half analog to digital converter of claim 12 wherein said sampled analog input voltage stored by said capacitor is integrated by said integrating means during said integration phase to generate said residual analog output voltage.

14. The bit-and-one-half analog to digital converter of claim 11 wherein said first bias current is a fractional portion of said second bias current.

15. The bit-and-one-half analog to digital converter of claim 11 wherein said first bias current is zero.

16. A multi-stage pipelined analog to digital converter, comprising:

a plurality of bit-and-one-half converter stages arranged in series, each converter stage receiving an analog input voltage and generating a residual analog output voltage, wherein each converter stage further comprises;

switched capacitor means, including an integrating means for integrating signals input thereto, for receiving said analog input voltage and for generating said residual analog output voltage, wherein said switched capacitor means samples said analog input voltage during a sampling phase and generates said residual analog output voltage during an integration phase;

comparing means for generating a digital stage output based on said residual analog output voltage generated by said switched capacitor means;

current means that communicates with said integrating means for supplying a first bias current to said integrating means during said sampling phase and a second bias current that is greater than said first bias current to said operation amplifier during said integration phase; and

correction means for accepting said digital stage output from each of said converter stages and for generating a corresponding digital output.

17. The multi-stage pipelined analog to digital converter of claim 16 wherein said switched capacitor means includes a capacitor that stores said sampled analog input voltage during said sampling phase.

18. The multi-stage pipelined analog to digital converter of claim 17 wherein said sampled analog input voltage stored by said capacitor is integrated by said integrating means during said integration phase to generate said residual analog output voltage.

19. The multi-stage pipelined analog to digital converter of claim 16 wherein said first bias current is a fractional portion of said second bias current.

20. The multi-stage pipelined analog to digital converter of claim 16 wherein said first bias current is zero.

21. A method of operating a bit-and-one-half analog to digital converter, comprising:

sampling an analog input voltage during a sampling phase;

generating a residual analog output voltage during an integration phase using an opamp;

generating a digital output based on said residual analog output voltage; and

supplying a first bias current to said opamp during said sampling phase and a second bias current that is greater than said first bias current to said opamp during said integration phase.

22. The method of claim 21 further comprising using a capacitor to store said sampled analog input voltage during said sampling phase.

23. The method of claim 22 further comprising integrating said sampled analog input voltage stored by said capacitor using said opamp during said integration phase to generate said residual analog output voltage.

24. The method of claim 21 wherein said first bias current is a fractional portion of said second bias current.

25. The method of claim 21 wherein said first bias current is zero.