Reference sensing circuit
First Claim
1. A sense amplifier reference voltage generator circuit for nonvolatile memory devices, comprising:
- at least one sense amplifier bias reference voltage generator (SABRVG) for generating a reference voltage at a reference node;
a start-up bias reference voltage generator (SBRVG) coupled to the SABRVG at the reference point;
a monitor reference voltage generator (MRVG) for generating a monitor reference voltage; and
a comparison module for comparing the monitor reference voltage with the reference voltage to produce a start-up control signal,wherein the SBRVG enhances a discharging speed of the reference voltage during a reading cycle of the nonvolatile memory and when the monitor reference voltage and the reference voltage are matched, the start-up control signal stops the SBRVG from operating, thereby having the SABRVG maintain the reference voltage.
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Accused Products
Abstract
A reference voltage generator circuit for nonvolatile memory devices is disclosed. The circuit has at least one sense amplifier bias reference voltage generator (SABRVG) for generating a reference voltage at a predetermined reference point that is coupled to a start-up bias reference voltage generator (SBRVG). It also includes a monitor reference voltage generator (MRVG) for generating a monitor reference voltage, and a comparison module for comparing the monitor reference voltage with the reference voltage to produce a start-up control signal, wherein the SBRVG enhances a changing speed of the reference voltage during a reading cycle of the nonvolatile memory and when the monitor reference and the reference voltages are matched, the start-up control signal stops the SBRVG from operating, thereby having the SABRVG maintain the reference voltage.
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Citations
17 Claims
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1. A sense amplifier reference voltage generator circuit for nonvolatile memory devices, comprising:
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at least one sense amplifier bias reference voltage generator (SABRVG) for generating a reference voltage at a reference node; a start-up bias reference voltage generator (SBRVG) coupled to the SABRVG at the reference point; a monitor reference voltage generator (MRVG) for generating a monitor reference voltage; and a comparison module for comparing the monitor reference voltage with the reference voltage to produce a start-up control signal, wherein the SBRVG enhances a discharging speed of the reference voltage during a reading cycle of the nonvolatile memory and when the monitor reference voltage and the reference voltage are matched, the start-up control signal stops the SBRVG from operating, thereby having the SABRVG maintain the reference voltage. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A reference voltage generator circuit for nonvolatile memory devices, comprising:
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at least one bias reference voltage generator (BRVG) for generating a reference voltage at a predetermined reference node thereof; a start-up bias reference voltage generator (SBRVG) coupled to the reference node, the SBRVG further comprising; a first pull-up pMOS transistor; a first NMOS transistor for functioning as a reference memory cell with its gate controlled by a wordline control signal; a second nMOS transistor connected in series with the first nMOS transistor with its gate controlled by a bitline control signal; and a control module coupled between the first pull-up pMOS transistor and the second nMOS transistor for turning on the SBRVG under a control of a start-up control signal; a monitor reference voltage generator (MRVG) for generating a monitor reference voltage; and a comparison module for comparing the monitor reference voltage with the reference voltage to produce the start-up control signal, wherein the SBRVG enhances a discharging speed of the reference voltage and when the monitor reference voltage and the reference voltage are matched, the start-up control signal stops the SBRVG from operating, thereby having the BRVG maintain the reference voltage. - View Dependent Claims (9, 10, 11, 12, 13)
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14. A method for enhancing reference voltage discharging speed during a reading cycle of a nonvolatile memory device, the method comprising:
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generating a bias reference voltage at a reference point by at least one sense amplifier bias reference voltage generator (SABRVG); enhancing the discharging speed of the bias reference voltage by coupling the reference point with a start-up bias reference voltage generator (SBRVG), the SBRVG further comprising; a first pull-up pMOS transistor; a first nMOS transistor for functioning as a reference memory cell with its gate controlled by a wordline control signal; a second nMOS transistor connected in series with the first nMOS transistor with its gate controlled by a bitline control signal; and a control module coupled between the first pull-up pMOS transistor and the second nMOS transistor for turning on the SBRVG under a control of a start- up control signal; generating a monitor reference voltage by a monitor reference voltage generator (MRVG); and comparing the monitor reference voltage with the reference voltage to produce the start-up control signal, wherein when the monitor reference and the reference voltages are matched, the start-up control signal stops the SBRVG from operating, thereby having the SABRVG maintain the reference voltage. - View Dependent Claims (15, 16, 17)
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Specification