Non-volatile semiconductor memory device and electric device with the same

• US 6,967,874 B2
• Filed: 06/08/2004
• Issued: 11/22/2005
• Est. Priority Date: 06/30/2003
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Hosono, Koji
• Primary Examiner(s): MAI, SON LUU
• Application Number:
  US10/862,538
• Publication Number:
  US 20050018489A1
• Time in Patent Office: 532 Days
• Field of Search: 365/185.33, 365/185.11, 365/185.12, 365/185.17, 365/185.25, 365/185.29
• US Class Current: 365/185.33
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/344 Arrangements for verifying correct erasure or for detecting overerased cells
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 8/10 Decoders

Abstract

A non-volatile semiconductor memory device includes: a cell array having electrically rewritable and non-volatile memory cells disposed at the respective intersections of word lines and bit lines intersecting each other; a row decoder circuit for selectively driving a word line of the cell array; a sense amplifier circuit disposed in communication with the cell array for data reading and writing; and a controller for executing sequence control of data write and erase, wherein in a data erase cycle controlled by the controller to erase memory cells disposed along at least one selected word line of the cell array, an adjacent/non-selected word line which is non-selected and adjacent to the selected word line in non-selected words lines in the cell array is precharged to a first erase-inhibition voltage, while the remaining non-selected word lines are precharged to a second erase-inhibition.

Claims

1. A non-volatile semiconductor memory device comprising:

a cell array having electrically rewritable and non-volatile memory cells disposed at the respective intersections of word lines and bit lines intersecting each other;

a row decoder circuit for selectively driving a word line of said cell array;

a sense amplifier circuit disposed in communication with said cell array for data reading and writing; and

a controller for executing sequence control of data write and erase, wherein

in a data erase cycle controlled by said controller to erase memory cells disposed along at least one selected word line of said cell array, an adjacent/non-selected word line which is non-selected and adjacent to said selected word line in non-selected word lines in said cell array is precharged to a first erase-inhibition voltage, while the remaining non-selected word lines are precharged to a second erase-inhibition voltage.

2. The non-volatile semiconductor memory device according to claim 1, wherein

said data erase cycle comprises:

a first precharge time for precharging said adjacent/non-selected word line to said first erase-inhibition voltage;

a second precharge time for precharging the remaining non-selected word lines to said second erase-inhibition voltage lower than said first erase-inhibition voltage after said first precharge time, while said adjacent/non-selected word line is held at said first erase-inhibition voltage; and

an erase time for erasing memory cells disposed along said selected word line after said second precharge time by applying an erase-permission voltage to said selected word line and applying an erase voltage to a semiconductor well on which said cell array is formed.

3. The non-volatile semiconductor memory device according to claim 1, wherein

said cell array comprises a plurality of NAND cell units arranged in a matrix manner therein, each NAND cell unit comprising a cell string with plural memory cells connected in series and driven by different word lines from each other, a first select gate transistor disposed for connecting one end of said string to a bit line and driven by a first select gate line disposed in parallel with said word lines, and a second select gate transistor disposed for connecting the other end of said string to a source line and driven by a second select gate line disposed in parallel with said word lines.

4. The non-volatile semiconductor memory device according to claim 3, wherein

said cell array comprises at least one block defined as a group of plural NAND cell units arranged in the direction of said word lines, said block being divided into at least two sub-blocks in the direction of said bit lines, and wherein

data erase is performed by each sub-block.

5. The non-volatile semiconductor memory device according to claim 4, wherein

said data erase cycle comprises:

a first precharge time for precharging an adjacent/non-selected word line disposed in a non-selected sub-block and adjacent to a selected sub-block to said first erase-inhibition voltage;

a second precharge time for precharging the remaining non-selected word lines to said second erase-inhibition voltage lower than said first erase-inhibition voltage after said first precharge time, while said adjacent/non-selected word line is held at said first erase-inhibition voltage; and

an erase time for erasing memory cells in said selected sub-block after said second precharge time by applying an erase-permission voltage to one or more word lines in said selected sub-block and applying an erase voltage to a semiconductor well on which said cell array is formed.

6. The non-volatile semiconductor memory device according to claim 5, wherein

said row decoder circuit comprises:

a word line driver circuit having plural word line drivers for outputting driving voltages necessary for the respective word lines in said block; and

a transfer transistor array having plural transfer transistors for transferring said driving voltages to the respective word lines.

7. The non-volatile semiconductor memory device according to claim 6, wherein

each of said word line drivers comprises an output circuit for applying said erase-permission voltage to a selected word line and for applying said second erase-inhibition voltage to a non-selected word line, and wherein

ones of said plural word line drivers, which are in communication with word lines disposed at boundary areas in the respective sub-blocks, each comprises a transfer gate in addition to said output circuit for selectively transferring said first erase-inhibition voltage to a corresponding word line based on a sub-block select signal and a timing signal.

8. The non-volatile semiconductor memory device according to claim 5, wherein

said data erase cycle further comprises a verify-read time for detecting cell current carried from said source line to said bit line after said erase time with applying a verify judging voltage to word lines in the selected sub-block and a pass voltage to word lines in the unselected sub-block, the pass voltage being set to turn on cells without regard to cell data.

15. An electric card equipped with a memory system defined in claim 1.

16. An electric device comprising:

a card interface;

a card slot connected to said card interface; and

an electric card defined in claim 15 and electrically connectable to said card slot.

17. The electric device according to claim 16, wherein said electric device is a digital still camera.

9. A non-volatile semiconductor memory device comprising:

a cell array having a plurality of NAND cell units arranged in a matrix manner therein, each NAND cell unit comprising a cell string with electrically rewritable and non-volatile memory cells connected in series and driven by different word lines from each other, a first select gate transistor disposed for connecting one end of said cell string to a bit line and driven by a first select gate line disposed in parallel with said word lines, and a second select gate transistor disposed for connecting the other end of said cell string to a source line and driven by a second select gate line disposed in parallel with said word lines;

a row decoder circuit for selectively driving a word line of said cell array, said row decoder circuit precharging, in a data erase cycle for erasing memory cells disposed along at least one selected word line of said cell array, an adjacent/non-selected word line in non-selected words lines, which is non-selected and adjacent to said selected word line to a first erase-inhibition voltage and precharging the remaining non-selected word lines to a second erase-inhibition voltage in said data erase cycle;

a sense amplifier circuit disposed in communication with said cell array for data reading and writing; and

a controller for executing sequence control of data write and erase.

10. The non-volatile semiconductor memory device according to claim 9, wherein

said cell array comprises at least one block defined as a group of plural NAND cell units arranged in the direction of said word lines, said block being divided into at least two sub-blocks in the direction of said bit lines, and wherein

data erase is performed by each sub-block.

11. The non-volatile semiconductor memory device according to claim 9, wherein

said data erase cycle controlled by said controller comprises:

a first precharge time for precharging said adjacent/non-selected word line to said first erase-inhibition voltage;

a second precharge time for precharging the remaining non-selected word lines to said second erase-inhibition voltage lower than said first erase-inhibition voltage after said first precharge time, while said adjacent/non-selected word line is held at said first erase-inhibition voltage; and

an erase time for erasing memory cells disposed along said selected word line after said second precharge time by applying an erase-permission voltage to said selected word line and applying an erase voltage to a semiconductor well on which said cell array is formed.

12. The non-volatile semiconductor memory device according to claim 11, wherein

said data erase cycle controlled by said controller further comprises a verify-read time after said erase time for detecting cell current carried from said source line to said bit line by applying a verify-judgment voltage to word lines in a selected sub-block, and by applying a pass voltage to word lines in a non-selected sub-block, said pass voltage being possible to turn on cells without regard to cell data.

13. The non-volatile semiconductor memory device according to claim 10, wherein

said row decoder circuit comprises:

a word line driver circuit having plural word line drivers for outputting driving voltages necessary for the respective word lines in said block; and

a transfer transistor array having plural transfer transistors for transferring said driving voltages to the respective word lines.

14. The non-volatile semiconductor memory device according to claim 13, wherein

each of said word line drivers comprises an output circuit for applying said erase-permission voltage to a selected word line and for applying said second erase-inhibition voltage to a non-selected word line, and wherein

ones of said plural word line drivers, which are in communication with word lines disposed at boundary areas in the respective sub-blocks, each comprises a transfer gate in addition to said output circuit for selectively transferring said first erase-inhibition voltage to a corresponding word line based on a sub-block select signal and a timing signal.