Address scramble
First Claim
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1. A method for operating a memory cell array, the method comprising:
- assigning word lines of a memory cell array as addresses for writing sets of data thereto from a cache memory; and
scrambling addresses of said sets of data by writing a first chunk of said particular set of data from said cache memory to a first word line of said array, and writing a second chunk of said particular set of data from said cache memory to a second word line of said array, said first chunk comprising a first subset of said particular set of data and said second chunk comprising a second subset of said particular set of data.
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Abstract
A method for operating a memory cell array, the method comprising assigning word lines of a memory cell array as addresses for writing sets of data thereto from a cache memory, and scrambling addresses of the sets of data by writing a first chunk of the particular set of data from the cache memory to a first word line of the array, and writing a second chunk of the particular set of data from the cache memory to a second word line of the array, the first chunk comprising a first subset of the particular set of data and the second chunk comprising a second subset of the particular set of data.
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Citations
9 Claims
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1. A method for operating a memory cell array, the method comprising:
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assigning word lines of a memory cell array as addresses for writing sets of data thereto from a cache memory; and scrambling addresses of said sets of data by writing a first chunk of said particular set of data from said cache memory to a first word line of said array, and writing a second chunk of said particular set of data from said cache memory to a second word line of said array, said first chunk comprising a first subset of said particular set of data and said second chunk comprising a second subset of said particular set of data. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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Specification