Opaque memory region for I/O adapter transparent bridge

• US 6,968,415 B2
• Filed: 03/29/2002
• Issued: 11/22/2005
• Est. Priority Date: 03/29/2002
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Williams, Phillip G., Jackowski, Stefan P., Sheplock, John M., Bronson, Timothy C.
• Primary Examiner(s): Auve, Glenn A.
• Assistant Examiner(s): King, Justin
• Application Number:
  US10/113,299
• Publication Number:
  US 20030188076A1
• Time in Patent Office: 1,334 Days
• Field of Search: 710/302, 710/306, 710/260, 710/305, 710/29, 710/36, 710/52, 345/564, 711/2
• US Class Current: 710/306
• CPC Class Codes: G06F 13/4059 where the synchronisation uses buffers, e.g. for speed matching between buses

Abstract

An opaque memory region for a bridge of an I/O adapter. The opaque memory region is inaccessible to memory transactions which traverse the bridge either from a primary bus to secondary bus or secondary bus to primary bus. As a result, memory transactions which target the opaque memory region are ignored by the bridge, allowing for the same address to exist on both sides of the bridge with different data stored in each. The implementation of the opaque memory region provides a means to complete memory transactions within I/O adapter subsystem memory, hence, relieving host computer system memory resources. In addition, a number of I/O adapters can be used in a host computer system where the host and all the I/O devices use some of the same memory addresses.

Claims

1. A bridge for forwarding memory transactions between a primary bus and a secondary bus, the bridge comprising:

a memory address range reserver that claims a range of system memory;

an opaque memory region reserver that claims an opaque memory region of system memory, wherein the opaque memory region overlaps the range of system memory; and

a memory transaction forwarding module that;

a) forwards a memory transaction from the primary bus to the secondary bus only when the memory transaction falls within the range and outside of the opaque memory region, and

b) forwards a memory transaction from the secondary bus to the primary bus only when the memory transaction falls outside of the range and outside of the opaque memory region.

2. The bridge of claim 1, wherein when the range and the opaque memory region overlap, the memory transaction forwarding module treats the overlap as though it is part of the opaque memory region.

3. The bridge of claim 1, wherein the bridge is of a peripheral component interconnect (PCI) type.

4. The bridge of claim 1, wherein the bridge is of a peripheral component interconnect extended (PCIx) type.

5. The bridge of claim 1, wherein the bridge is part of an I/O adapter.

6. The bridge of claim 5, wherein the I/O adapter further comprises a processor, a memory, at least one PCI device and a PCI bus in communication with the bridge, the processor, the memory and the at least one PCI device.

7. The bridge of claim 6, wherein the secondary bus is part of the I/O adapter.

8. A method of forwarding memory transactions on a bridge between a primary and a secondary bus, the method comprising the steps of:

reserving a memory address range of system memory;

reserving an opaque memory region of system memory, wherein the opaque memory region overlaps the range of system memory; and

forwarding a memory transaction;

a) from the primary bus to the secondary bus only when the memory transaction falls within the range and outside of the opaque memory region, and

b) from the secondary bus to the primary bus only when the memory transaction falls outside of the range and outside of the opaque memory region.

9. The method of claim 8, wherein when the range and the opaque memory region overlap, forwarding occurs as though the overlap is the opaque memory region.

10. The method of claim 8, wherein the bridge is of a peripheral component interconnect (PCI) type.

11. The method of claim 8, wherein the bridge is of a peripheral component interconnect extended (PCIx) type.

12. The method of claim 8, wherein the bridge is part of an I/O adapter.

13. The method of claim 12, wherein the I/O adapter further comprises a processor, a memory, at least one PCI device and a PCI bus in communication with the bridge, the processor, the memory and the at least one PCI device.

14. The method of claim 12, wherein the secondary bus is part of the I/O adapter.

15. An input-output (I/O) adapter for communicating between a primary bus and a secondary bus, the I/O adapter comprising:

a bridge for forwarding memory transactions between the primary bus and the secondary bus, the bridge including;

a memory address range reserver that claims a range of system memory;

an opaque memory region reserver that claims an opaque memory region of system memory, wherein the opaque memory region overlaps the range of system memory; and

a memory transaction forwarding module that;

a) forwards a memory transaction from the primary bus to the secondary bus only when the memory transaction falls within the range and outside of the opaque memory region, and

b) forwards a memory transaction from the secondary bus to the primary bus only when the memory transaction falls outside of the range and outside of the opaque memory region.

16. The I/O adapter of claim 15, wherein when the range and the opaque memory region overlap, the memory transaction forwarding module treats the overlap as though it is part of the opaque memory region.

17. The I/O adapter of claim 15, wherein the bridge is of a peripheral component interconnect (PCI) type.

18. The I/O adapter of claim 15, wherein the bridge is of a peripheral component interconnect extended (PCIx) type.

19. The I/O adapter of claim 15, further comprising a processor, a memory, at least one PCI device and a PCI bus in communication with the bridge, the processor, the memory and the at least one PCI device.

20. The I/O adapter of claim 15, wherein the secondary bus is part of the I/O adapter.