Multiple server in-rush current reduction

• US 6,968,465 B2
• Filed: 06/24/2002
• Issued: 11/22/2005
• Est. Priority Date: 06/24/2002
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Ekrot, Alexander C., Freevol, Jason W.
• Primary Examiner(s): Lee, Thomas
• Assistant Examiner(s): Bae, Ji H.
• Application Number:
  US10/178,300
• Publication Number:
  US 20030237008A1
• Time in Patent Office: 1,247 Days
• Field of Search: 725/150, 713/310, 713/300, 713/330, 714/36, 375/354, 382/245, 323/908
• US Class Current: 713/300
• CPC Class Codes: G06F 1/30 Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations for resetting only G06F1/24
• CPC Class Codes: G06F 1/329 by task scheduling
• CPC Class Codes: H02H 9/001 limiting speed of change of electric quantities, e.g. soft switching on or off progressive control of electronic switches for eliminating interferences H03K17/16
• CPC Class Codes: Y10S 323/908 Inrush current limiters

Abstract

The specification discloses a system and related method for delaying the powering-on of a server after loss of power. In this way, each server in a rack of servers may have its power restored at staggered times to minimize in-rush current associated with start-up of the rack-mounted server system.

Claims

1. In a rack-mounted server system having a plurality of servers therein, a method comprising:

restoring the plurality of servers to an operational state automatically after a loss of power to the rack-mounted server system; and

delaying, selectively, powering on of a first server by implementing a selectable delay circuit coupled between a super input/output controller and a power supply for a power-on signal within the first server.

2. The method as defined in claim 1 further comprising setting a delay time for the selectable delay circuit.

3. The method as defined in claim 2 wherein selling a delay time for the selectable delay circuit further comprises actuating dip switches within the first server that control delay time of the selectable delay circuit.

4. The method as defined in claim 2 wherein setting a delay time for the first sewer further comprises executing a software program to selectively set bits in a non-volatile memory that control delay time in the selectable delay circuit.

5. The method as defined in claim 4 wherein executing a software program to selectively set bits in a non-volatile memory that control delay time in the selectable delay circuit further comprises generating a random number, and selectively setting bits in the non-volatile memory based on the random number.

6. The method as defined in claim 4 wherein executing a software program to selectively set bits in a non-volatile memory that control delay time in the selectable delay circuit further comprises setting bits in the non-volatile memory based on a serial number of the first server.

7. The method as defined in claim 1 further comprising delaying, selectively, powering on of a second server, wherein a power-on delay time for the first server and a power-on delay time for the second server are different.

8. The method as defined in claim 7 wherein delaying, selectively, powering on the first and second servers further comprises:

delaying, for the power-on delay time for the first server, the power-on signal issued by the super input/output controller to the power supply of the first server; and

delaying, for the power-on delay time for the second server, a power-on signal issued by a super input/output controller to a power supply of the second server.

9. The method as defined in claim 8 wherein the delaying steps further comprise implementing a selectable delay circuit between the super input/output controller and the power supply for the power-on signals one each in the first and second server, and wherein the selectable delay circuits provide a programmable delay of the power-on signals propagating between the super input/output controllers and the power supplies of the first and second servers.

10. A rack-mounted server system comprising:

a first sewer mounted in the rack-mounted server system, the first server further composing

a super input/output controller having a power-on output signal;

a power supply having a power-on input signal, and wherein the power supply turns on in response to assertion of the power-on input signal; and

a delay circuit coupling the power-on output signal of the super input/output controller to the power-on input signal of the power supply, and wherein the delay circuit provides an adjustable delay of an asserted state of the power-on output signal;

a second server mounted in the rack-mounted server system; and

wherein the first and second servers are configured to automatically power-on at different times when power is restored to the rack-mounted server system after loss of power, when the first and second servers were in full operation at the loss of power.

11. The system as defined in claim 10 wherein the delay circuit further comprises:

a timer circuit, and wherein the timer circuit asserts a timer output signal at a predetermined time after return of auxiliary power to each of the first server and the second server; and

a latch circuit coupled to the timer output signal and the power-on output signal of the super input/output controller, and wherein the latch circuit latches an asserted state of the power-on output signal and allows the asserted state of the power-on output signal to propagate to the power supply upon assertion of the timer output signal.

12. The system as defined in claim 11 wherein the timer circuit further comprises:

an oscillator producing a clock signal;

a counter coupled to the clock signal and producing a count output signal;

a set of count setpoint signals; and

a comparator coupled to the count output signal and the setpoint signals, and wherein the comparator asserts the timer output signal when the count output signals match the setpoint signals.

13. The system as defined in claim 12 wherein the clock signal produced by the oscillator has a frequency of four Hertz.

14. The system as defined in claim 12 wherein the count output signal of the counter is a three bit signal.

15. The system as defined in claim 12 wherein the setpoint signal is a three bit signal.

16. The system as defined in claim 11 wherein the timer circuit further comprises:

a microcontroller coupled to a secondary expansion bus in each of the first server and the second server;

a non-volatile memory coupled to the microcontroller;

a serial-to-parallel conversion device coupled to the microcontroller by way of a serial transfer line; and

wherein the microcontroller reads the non-volatile memory and transfers a setpoint signal serially to the serial-to-parallel device, and wherein the serial-to-parallel device converts the setpoint for use by the comparator.

17. The system as defined in claim 12 wherein the timer circuit further comprises a set of electrical switches each having a first pole coupled to ground and a second pale coupled to a power source through a pull-up resistor, the second pole of each switch coupled to the comparator and forming the setpoint signals.

18. A server for use in a rack-mounted server system comprising:

a microprocessor;

a main memory array;

a bridge device coupling the microprocessor and the main memory array;

a mass storage device coupled to the bridge device;

a controller coupled to the bridge device, and also coupled to a front panel power button, wherein the controller is configured to assert a power-on output signal when the front panel power button is actuated, and wherein the controller is further configured to assert the power-on output signal to bring the server to its prior operational state after a loss of power;

a delay circuit coupling the power-on output signal from the controller to a power supply, and wherein the delay circuit is configured to programmably delay an assertion of the power-on output signal to the power supply.

19. The system as defined in claim 18 wherein the delay circuit further comprises:

a timer circuit, and wherein the timer circuit asserts a timer output signal at a predefined time after return of auxiliary power to the server; and

a latch circuit coupled to the timer output signal and the power-on output signal of the controller, and wherein the latch circuit latches an asserted state of the power-on output signal and allows the asserted state of the power-an output signal to propagate the power supply upon assertion of the timer output signal.

20. The system as defined in claim 19 wherein the timer circuit further comprises:

an oscillator producing a clock signal;

a counter coupled to the clock signal and producing a count output signal;

a set of count setpoint signals; and

a comparator coupled to the count output signal and the setpoint signals, and wherein the comparator asserts the timer output signal when the count output signals match the setpoint signals.

21. The system as defined in claim 20 wherein the clock signal produced by the oscillator has a frequency of four Hertz.

22. The system as defined in claim 20 wherein the count output signal of the counter is a three bit signal.

23. The system as defined, in claim 20 wherein the setpoint signal is a three bit signal.

24. The system as defined in claim 19 wherein the timer circuit further comprises:

a microcontroller coupled to a secondary expansion bus of the server;

a non-volatile memory coupled to the microcontroller;

a serial-to-parallel conversion device coupled to the microcontroller by way of a serial transfer line; and

wherein the microcontroller reads the non-volatile memory and transfers a setpoint signal serially to the serial-to-parallel device, and wherein the serial-to-parallel device converts the setpoint for use by the comparator.

25. The system as defined in claim 20 wherein the timer circuit further comprises a set of electrical switches each having a first pole coupled to ground and a second pole coupled to a power source through a pull-up resistor, the second pole of each switch coupled to the comparator and forming the setpoint signals.

26. A computer for use as a server in a rack-mounted server system comprising:

a microprocessor;

a main memory array;

a bridge device coupling the microprocessor and the main memory array;

a mass storage device coupled to the bridge device;

a super input/output (super I/O) controller coupled to the bridge device, and also coupled to a front panel power button, wherein the super I/O controller is configured to assert a power-on output signal when the front panel power button is actuated, and wherein the super I/O controller is further configured to assert the power-on output signal to bring the server to its prior operational state after a loss of power;

a means for selectively delaying an assertion of the power-on output signal to a power supply, the means for selectively delaying coupling the power-on output signal from the super I/O controller to the power supply.

27. The system as defined in claim 26 wherein the means for selectively delaying further comprises a delay circuit coupled between the super I/O controller and the power supply, and wherein the delay circuit is adapted to provide an adjustable delay of the propagation of an asserted state of the power-on output signal to the power supply.

28. The system as defined in claim 27 wherein the delay circuit further comprises:

a timer circuit, and wherein the timer circuit asserts a timer output signal at a predefined time after return of auxiliary power to the server; and

a latch circuit coupled to the timer output signal and the power-on output signal of the super I/O controller, and wherein the latch circuit latches an asserted state of the power-on output signal and allows the asserted state of the power-on output signal to propagate the state the power supply upon assertion of the timer output signal.

29. The system as defined in claim 28 wherein the timer circuit further comprises:

an oscillator producing a clock signal;

a counter coupled to the clock signal and producing a count output signal;

a set of count setpoint signals; and

a comparator coupled to the count output signal and the setpoint signals, and wherein the comparator asserts the timer output signal when the count output signals match the setpoint signals.

30. The system as defined in claim 29 wherein the clock signal produced by the oscillator has a frequency of four Hertz.

31. The system as defined in claim 29 wherein the count output signal of the counter is a three bit signal.

32. The system as defined in claim 29 wherein the setpoint signal is a three bit signal.

33. The system as defined in claim 28 wherein the timer circuit further comprises:

a microcontroller coupled to a secondary expansion bus of the server;

a non-volatile memory coupled to the microcontroller;

a serial-to-parallel conversion device coupled to the microcontroller by way of a serial transfer line; and

wherein the microcontroller reads the non-volatile memory and transfers a setpoint signal serially to the serial-to-parallel device, and wherein the serial-to-parallel device converts the setpoint for use by the comparator.

34. The system as defined in claim 29 wherein the timer circuit further comprises a set of electrical switches each having a first pole coupled to ground and a second pole coupled to a power source through a pull-up resistor, the second pole of each switch coupled to the comparator and forming the setpoint signals.