Semiconductor device

• US 6,969,662 B2
• Filed: 06/05/2002
• Issued: 11/29/2005
• Est. Priority Date: 06/18/2001
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Innovative Silicon ISI SA
• Inventors: Fazan, Pierre, Okhonin, Serguei
• Primary Examiner(s): Pham, Long
• Assistant Examiner(s): Louie, Wai-Sing
• Application Number:
  US10/450,238
• Publication Number:
  US 20040021137A1
• Time in Patent Office: 1,273 Days
• Field of Search: 438128-132, 438197-199, 438/292, 438/587, 438/982, 365/185.08, 365/185.14, 365/185.25, 365/185.26, 365/189.04
• US Class Current: 438/292
• CPC Class Codes: G11C 11/403 with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H04N 25/772 comprising A/D, V/T, V/F, I/T or I/F converters
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/01 Manufacture or treatment
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: Y10S 257/905 Plural dram cells share common contact or common trench
• CPC Class Codes: Y10S 257/907 Folded bit line dram configuration
• CPC Class Codes: Y10S 438/982 Varying orientation of devices in array

Abstract

A semiconductor device, such as a memory device or radiation detector, is disclosed, in which data storage cells are formed on a substrate 13. Each of the data storage cells includes a field effect transistor having a source 18, drain 22 and gate 28, and a body arranged between the source and drain for storing electrical charge generated in the body. The magnitude of the net electrical charge in the body 22 can be adjusted by input signals applied to the transistor, and the adjustment of the net electrical charge by the input signals can be at least partially cancelled by applying electrical voltage signals between the gate 28 and the drain 22 and between the source 18 and the drain 22.

Claims

1. A method of controlling a memory device including at least one transistor to constitute a memory cell, wherein the transistor is adapted to maintain a first data state and a second data state, and wherein the transistor includes:

a source region formed adjacent to the body region,

a drain region formed adjacent to the body region,

a body region disposed between the source region and the drain region wherein the body region is electrically floating, and

a gate disposed over the body region, the method comprising;

applying a first voltage to the gate of the transistor;

applying a second voltage to the drain region of the transistor;

removing the second voltage from the drain region;

removing the first voltage from the gate wherein the first voltage is removed from the gate after removing the second voltage from the drain region; and

storing a first charge in the body region in response to removing the second voltage from the drain region or the first voltage from the gate, wherein the first charge is representative of the first data state.

2. The method of claim 1 wherein, in response to the first and second voltages, majority carriers are removed from the body region.

3. The method of claim 1 further including causing a channel current to flow from the drain region to the source region in response to the first and second voltages.

4. The method of claim 3, further including terminating the channel current in response to removing the first voltage.

5. The method of claim 1 further including applying a third voltage to the gate after removing the first voltage from the gate.

6. The method of claim 5 wherein the third voltage is ground.

7. The method of claim 1 wherein, in response to the first and second voltages, majority carriers accumulate in the body region via impact ionization.

8. The method of claim 1 further including:

applying a third voltage to the drain region;

applying a fourth voltage to the gate;

creating a second charge in the body region in response to applying the third voltage to the drain region and the fourth voltage to the gate, wherein the second charge is representative of the second data state;

removing the third voltage from the drain region;

removing the fourth voltage from the gate; and

storing the second charge in the body region in response to removing the third voltage from the drain region or the fourth voltage from the gate.

9. The method of claim 8 further including applying a fifth voltage to the gate after removing the fourth voltage from the gate.

10. The method of claim 9 wherein the fifth voltage is ground.

11. The method of claim 9 further including applying a fifth voltage to the drain region after removing the third voltage from the drain region.

12. The method of claim 11 wherein the fifth voltage is ground.

13. The method of claim 8 wherein the second voltage is equal to the third voltage.

14. A method of controlling a memory device including at least one transistor to constitute a memory cell, wherein the transistor is adapted to maintain a first data state and a second data state, and wherein the transistor includes:

a source region formed adjacent to the body region,

a drain region formed adjacent to the body region,

a body region disposed between the source region and the drain region wherein the body region is electrically floating, and

a gate disposed over the body region, the method comprising;

applying a first voltage to the gate of the transistor;

applying a second voltage to the drain region of the transistor, wherein the second voltage is less than the first voltage;

applying a third voltage to the source region of the transistor, wherein the third voltage is less than the first voltage

removing the second voltage from the drain region; and

removing the first voltage from the gate wherein the first voltage is removed from the gate after removing the second voltage from the drain region.

15. The method of claim 14 further including storing a first charge in the body region in response to removing the second voltage from the drain region or the first voltage from the gate, wherein the first charge is representative of the first data state.

16. The method of claim 14 wherein the third voltage is ground.

17. The method of claim 14 further including causing a channel current to flow from the drain region to the source region in response to the first, second and third voltages.

18. The method of claim 17 further including terminating the channel current in response to removing the first voltage.

19. The method of claim 14 further including applying the third voltage to the gate after removing the first voltage from the gate.

20. The method of claim 14 further including applying the third voltage to the drain region after removing the first voltage from the gate, wherein the third voltage is ground.

21. The method of claim 14 wherein the second voltage is applied to the drain region after applying the first voltage to the gate.

22. The method of claim 14 wherein the second voltage is applied to the drain region before applying the first voltage to the gate.

23. The method of claim 14 wherein the second voltage is applied to the drain region when the first voltage is applied to the gate.

24. A method of controlling a memory device including at least one transistor to constitute a memory cell, wherein the transistor includes:

a source region formed adjacent to the body region,

a drain region formed adjacent to the body region,

a body region disposed between the source region and the drain region wherein the body region is electrically floating, and

a gate disposed over the body region, the method comprising;

applying and maintaining a first voltage on the gate of the transistor;

applying and maintaining a second voltage on the drain region of the transistor, wherein the second voltage is applied to the drain region after applying the first voltage to the gate and wherein the second voltage is less than the first voltage;

storing a first charge in the body region, wherein the first charge is representative of a first data state;

removing the second voltage from the drain region; and

removing the first voltage from the gate wherein the first voltage is removed from the gate after removing the second voltage from the drain region.

25. The method of claim 24 further including applying a third voltage to the drain region after removing the first voltage from the gate.

26. The method of claim 25 further including applying a third voltage to the gate after removing the first voltage from the gate.

27. The method of claim 26 wherein the third voltage is ground.

28. The method of claim 27 further including applying the third voltage to the source region of the transistor.

29. The method of claim 24 further including applying a third voltage to the drain region before removing the first voltage from the gate wherein the third voltage is ground.

30. The method of claim 29 wherein, in response to the first and second voltages, a conduction channel, comprised of minority carriers, forms in the body region between the source and drain regions thereby causing a channel current to flow in the body region between the source and drain regions.

31. The method of claim 24 further including applying a third voltage to the gate after removing the first voltage from the gate wherein the first voltage is greater than the third voltage.

32. The method of claim 24 further including storing a first charge in the body region in response to removing the second voltage from the drain region or the first voltage from the gate, wherein the first charge is representative of a first data state of the transistor.

33. The method of claim 32 further including causing a channel current to flow from the drain region to the source region in response to the first and second voltages.

34. The method of claim 33 further including terminating the channel current in response to removing the first voltage.

35. The method of claim 32 further including applying a third voltage to the gate after removing the first voltage from the gate and wherein the third voltage is ground.

36. The method of claim 35 further including applying a third voltage to the drain region after removing the first voltage from the gate.

37. The method of claim 32 wherein, in response to the first and second voltages, majority carriers are accumulate to the body region via impact ionization.

38. The method of claim 24 further including:

applying a third voltage to the drain region;

applying a fourth voltage to the gate;

creating a second charge in the body region in response to applying the third voltage to the drain region and the fourth voltage to the gate, wherein the second charge is representative of a second data state of the transistor;

removing the third voltage from the drain region;

removing the fourth voltage from the gate; and

storing the second charge in the body region in response to removing the third voltage from the drain region or the fourth voltage from the gate.

39. The method of claim 38 further including applying a fifth voltage to the gate after removing the fourth voltage from the gate.

40. The method of claim 39 wherein the fifth voltage is ground.

41. The method of claim 39 further including applying a fifth voltage to the drain region after removing the third voltage from the drain region.

42. The method of claim 41 wherein the fifth voltage is ground.

43. The method of claim 38 wherein the second voltage is equal to the third voltage.