Backthinned CMOS sensor with low fixed pattern noise

• US 6,969,839 B2
• Filed: 01/31/2003
• Issued: 11/29/2005
• Est. Priority Date: 01/31/2003
• Status: Active Grant

• Current Assignee: Eotech, LLC
• Original Assignee: Intevac
• Inventors: Costello, Kenneth A
• Primary Examiner(s): Luu, Thanh X.
• Application Number:
  US10/355,836
• Publication Number:
  US 20040149888A1
• Time in Patent Office: 1,033 Days
• Field of Search: 250/214.1, 250/208.1, 257/228, 257/447, 257/460
• US Class Current: 250/214.1
• CPC Class Codes: H01L 27/14618 Containers
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

This invention deals with the reduction in fixed pattern noise in backthinned CMOS imagers primarily for use in a vacuum environment. Reduction is achieved by effectively shielding the imager. This is done by depositing a conductive layer on the front surface prior to the attachment of a support member or by incorporating a conductive layer into the die at least extensive with the analog circuitry. This also may be achieved by leaving a void adjacent to the analog circuitry area. This void, filled with air or a vacuum specifies a low dielectric layer over critical analog circuitry. Finally there is extended across the die an adhesive or underfill material after which a support member is placed onto the underfill to provide structure to the die. The underfill and the support layer should have thermal coefficients of expansion that substantially match that of the silicon.

Claims

1. A CMOS chip for use in an imaging system while avoiding fixed pattern noises comprising

a die comprising an array of pixel sensors and analog and digital support electronics at the front surface of said die,

a silicon layer at the back surface of said die,

a support structure for the chip on the front surface comprising a conductive shield in direct contact with said front surface of said chip at least overlying said analog support electronics and said array of pixel sensors of said die to reduce fixed pattern noises, said support structure to maintain the shape and configuration of the chip when said silicon back surface layer is thinned to an epitaxial layer at least in areas corresponding to said array of pixel sensors for imaging exposure of said pixels through said thinned epitaxial layer.

2. The CMOS chip of claim 1 in which conductive shield comprises aluminum.

3. The CMOS chip of claim 2 in which the aluminum is about 1000 angstroms thick.

4. The CMOS chip of claim 1 in which said conductive shield is deposited by a sputtering process.

5. The CMOS chip of claim 1 in which the conductive shield is thermally evaporated onto the front surface of the die.

6. A CMOS chip for use in an imaging system with reduced fixed pattern noise consisting essentially of a die comprising,

a silicon layer at the back surface of said die supporting a pixel addressing and analog support electronics for said die,

a support structure for the chip on the front surface of said die directly in contact with the front surface of said chip including a conductive shield positioned at least overlying the pixel addressing and analog support electronics of said die to maintain the shape and configuration of the chip when the back surface silicon layer has been thinned to an epitaxial surface layer for exposure of said pixel addressing electronics through said epitaxial surface layer and to reduce fixed pattern noise during imaging, said support structure at the front surface of said die comprising an adhesive underfill material and a front surface support layer in which said adhesive and said support layer each have a thermal coefficient of expansion generally matching the thermal coefficient of expansion of the silicon layer at the back surface of said die.

7. The CMOS chip of claim 6 in which said conductive shield is sufficiently robust as to cover the front surface of the chip including the active pixel array to block greater than about 80% of the light incident on the front surface of the die from reaching the pixels of the chip.

8. An imaging system with reduced fixed pattern noises comprising placing a CMOS chip comprising:

a die consisting essentially of an array of pixel sensors and analog and digital support electronics at its front surface positioned on a silicon layer at its back surface;

a conductive shield positioned at the front surface of said die at least overlying said pixel sensors and analog support electronics of said die to reduce fixed pattern noise during imaging;

said conductive shield being positioned on an adhesive underfill material positioned on the front surface side of said die underlying a supporting layer;

said conductive shield, said underfill material and said supporting layer comprising a support structure for the chip on the front surface thereof to maintain the shape and configuration of the chip when said silicon layer on the back side of said die is thinned to an epitaxial surface layer, said conductive shield and said underfill material each having a thermal coefficient of expansion generally matching the thermal coefficient of expansion of the silicon layer at the back surface of said die;

in position in a proximity focused imaging system comprising;

a photocathode mounted on a transparent base;

the CMOS chip; and

a vacuum system between the photocathode and the CMOS chip with the back surface of the CMOS chip facing said photocathode and said photocathode and said CMOS chip positioned within the vacuum facing each other, the incoming electron image from the facing photocathode feeding to the back surface of said CMOS chip; and

exposing said photocathode to a light image as to cause electrons from said photocathode to travel to the back surface of said CMOS chip.

9. A CMOS chip for use in an imaging system with reduced fixed pattern noise comprising a die comprising,

a silicon layer at the back surface of said die supporting a pixel addressing or analog support electronics for said die,

a support structure for the chip on the front surface of said die including a conductive shield positioned at least overlying the pixel addressing or analog support electronics of said die to maintain the shape and configuration of the chip when the back surface silicon layer has been thinned to an epitaxial surface layer and to reduce fixed pattern noise during imaging, said support structure at the front surface of said die comprising an adhesive underfill material and a front surface support layer in which said adhesive and said support layer each have a thermal coefficient of expansion generally matching the thermal coefficient of expansion of the silicon layer at the back surface of said die

said adhesive material including a void between said support layer and said front surface of said die over that portion of the chip associated with pixel addressing or analog support electronics.