Planarized and silicided trench contact

• US 6,969,888 B2
• Filed: 01/29/2004
• Issued: 11/29/2005
• Est. Priority Date: 03/05/2003
• Status: Active Grant

• Current Assignee: Advanced Analogic Technologies Incorporated (Skyworks Solutions Incorporated)
• Original Assignee: Advanced Analogic Technologies Incorporated (Skyworks Solutions Incorporated)
• Inventors: Williams, Richard K., Chan, Wai Tien, Cornell, Michael E.
• Primary Examiner(s): Eckert, George
• Assistant Examiner(s): Ortiz, Edgardo
• Application Number:
  US10/768,280
• Publication Number:
  US 20040183136A1
• Time in Patent Office: 670 Days
• Field of Search: 257329-332, 257/383, 257/341, 438/259, 438270-271, 438/589
• US Class Current: 257/341
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4925 with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with only a vertical doping structure or vertical doping variation H01L29/4916
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/4941 with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Power MOSFETs and fabrication processes for power MOSFETs use a continuous conductive gate structure within trenches to avoid problems arising from device topology caused when a gate bus extends above a substrate surface. The gate bus trench and/or gate structures in the device trenches can contain a metal/silicide to reduce resistance, where polysilicon layers surround the metal/silicide to prevent metal atoms from penetrating the gate oxide in the device trenches. CMP process can remove excess polysilicon and metal and planarize the conductive gate structure and/or overlying insulating layers. The processes are compatible with processes forming self-aligned or conventional contacts in the active device region.

Claims

1. A power MOSFET comprising:

a substrate comprising a first trench and a second trench extending from a top surface of the substrate, wherein the first trench is deeper than the second trench;

a source region, a channel region, and a drain region in the substrate and arranged vertically along at least a portion of a wall of the trench;

a gate structure that extends continuously in the first and second trenches, wherein a top surface of the gate structure does not extend above the top surface of the substrate, a first portion of the gate structure acts as a gate of a vertical device in the wall of the first trench, and a second portion of the gate structure forms a gate bus that includes a metal/silicide region and resides in the second trench; and

a gate contact that contacts the gate bus.

2. The power MOSFET of claim 1, wherein the second trench is wider than the first trench.

3. The power MOSFET of claim 1, further comprising a dielectric material residing in the first and second trenches above the gate structure, wherein a top surface of the dielectric material is coplanar with the top surface of the substrate.

4. The power MOSFET of claim 1, further comprising a metal layer that is patterned to form a source contact that overlies the first trench and contacts the source region adjacent to the first trench and the gate contact that contacts the gate bus.

5. The power MOSFET of claim 1, wherein the gate structure comprises a continuous polysilicon region that extends from the first trench to the second trench.

6. The power MOSFET of claim 1, wherein the metal/silicide region extends continuously from the second trench into the first trench.

7. The power MOSFET of claim 6, further comprising:

a gate insulator in the first trench between the gate structure and the wall containing the channel region; and

polysilicon that is in the first trench and isolates the metal/silicide region from the gate insulator.

8. The power MOSFET of claim 7, wherein the polysilicon comprises a first polysilicon layer in the first trench and underlying the metal/silicide region;

and a second polysilicon layer in the first trench and overlying the metal/silicide region.

9. The power MOSFET of claim 1, wherein the second portion of the gate structure further comprises:

a first polysilicon layer in the second trench and underlying the metal/silicide region; and

a second polysilicon layer in the second trench and overlying the metal/silicide region.

10. A power MOSFET comprising:

a substrate comprising a first trench and a second trench extending from a top surface of the substrate;

a source region, a channel region, and a drain region in the substrate and arranged vertically along at least a portion of a wall of the first trench;

a gate insulator in the first trench along the wall containing the channel region; and

a gate structure that extends continuously in the first and second trenches, wherein a first portion of the gate structure acts as a gate of a vertical device in the wall of the first trench, and a second portion of the gate structure that is in the second trench forms a gate bus, the first portion of the gate structure comprising;

a metal/silicide region in the first trench; and

polysilicon that is in the first trench and between the metal/silicide region and the gate insulator.

11. The power MOSFET of claim 10, wherein the polysilicon comprises:

a first polysilicon layer that underlies the metal/silicide region; and

a second polysilicon layer that overlies the metal/silicide region, wherein

the combination of the first and second polysilicon layers isolate the metal/silicide layer from the gate insulator.

12. The power MOSFET of claim 10, wherein the metal/silicide region extends continuously from the first trench into the second trench.

13. The power MOSFET of claim 12, wherein the polysilicon extends continuously from the first trench into the second trench.

14. The power MOSFET of claim 10, wherein the first trench is deeper than the second trench.

15. The power MOSFET of claim 14, wherein the second trench is wider than the first trench.

16. The power MOSFET of claim 10, wherein the second trench is wider than the first trench.

17. The power MOSFET of claim 10, further comprising a gate contact that contacts the gate bus.

18. The power MOSFET of claim 10, further comprising a dielectric material residing in the first and second trenches above the gate structure, wherein a top surface of the dielectric material is coplanar with the top surface of the substrate.

19. The power MOSFET of claim 18, further comprising a metal layer that is patterned to form a source contact that overlies the first trench and contacts the source region adjacent to the first trench and the gate contact that contacts the gate bus.