Multiple mode switching regulator having an automatic sensor circuit for power reduction

• US 6,969,979 B2
• Filed: 03/09/2004
• Issued: 11/29/2005
• Est. Priority Date: 03/09/2004
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Baldwin, David J., Kohout, James A.
• Primary Examiner(s): BERHANE, ADOLF D
• Application Number:
  US10/797,780
• Publication Number:
  US 20050200341A1
• Time in Patent Office: 630 Days
• Field of Search: 323/265, 323/269, 323/282, 323/284, 323/351
• US Class Current: 323/282
• CPC Class Codes: H02M 1/0032 Control circuits allowing low power mode operation, e.g. in standby mode
• CPC Class Codes: H02M 3/158 including plural semiconductor devices as final control devices for a single load
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A switching regulator having a control circuit that automatically senses when a low power mode should be initiated without the use of expensive external components nor an extensive amount of external components is disclosed herein. The switching regulator includes an input switching device, a driver, an inductor, a first output switching device, a second output switching device and an output node. The control circuit includes a low power switching device connected to the output node and the second end of the inductor. An amplifier connects the low power switching device and the first output switching device. A first current mirror couples to the amplifier to mirror the difference between the output current through the output load and the current supplied at the second end of the inductor. A second current mirror couples to the first current mirror to mirror the current difference through a current source and a capacitor connected in parallel across the current source. A comparator compares the voltage generated by the capacitor with a predetermined voltage source. A first and second AND gate couples to the comparator. The output of the first AND gate provides a entry signal that initiates the low power mode for the switching regulator. The second AND gate couples to receive this entry signal. The output of the first AND gate provides a exit signal that indicates when the switching regulator is not in low power mode. The first AND gate couples to receive this exit signal.

Claims

1. A switching regulator, comprising:

a driver coupled to receive a first high side control signal;

an input switching device having a source node, a drain node, and a control node, the control node coupled to an output of the driver, the drain node coupled to receive an input voltage;

a diode coupled between the source node of the input switching device and ground;

an inductor having a first end coupled to the source node of the input switching device;

a first output switching device having a drain node coupled to the second end of the inductor, the first output switching device having a control node coupled to a second high side control signal;

a second output switching device having a drain node coupled to the second end of the inductor, the second output switching device having a control node coupled to a low side control signal, the second output switching device having a source node coupled to ground;

an output load coupled between the source nodes of the first and second output switching devices;

an output capacitor coupled between the source nodes of the first and second output switching devices to provide an output voltage; and

a low power control circuit coupled across the inductor, wherein the low power control circuit monitors the current delivered to the output load and automatically initiates the low power mode of the switching regulator independent of the value of the output voltage, the output capacitor, the inductor and the input voltage.

2. A switching regulator as recited in claim 1, wherein the low power control circuit comprises:

a low power switching device having a control node coupled to receive the high side control signal and a drain node coupled to the second end of the inductor;

an amplifier coupled to the source node of the low power switching device and the first output switching device;

a first current mirror coupled to the amplifier to mirror the output current delivered to the output load through the low power switching device;

a second current mirror coupled to the first current mirror;

a current source coupled between the second current mirror and ground;

a capacitor coupled across the current source;

a comparator coupled to the second current mirror and coupled to receive a predetermined voltage source to compare the voltage across the capacitor with the predetermined voltage source;

a first AND gate coupled to the comparator and to receive the low power mode signal;

an inverter coupled to receive the low power mode signal to generate an inverted low power mode signal;

a second AND gate coupled to the comparator and to receive the inverted low power mode signal and the inductive switch signal;

a first counter, having an input and an output, the input coupled to the first AND gate to provide a low power entry signal at the output, the output coupled to the second AND gate; and

a second counter, having an input and an output, the input coupled to the second AND gate to provide a low power exit signal at the output, the output coupled to the first AND gate.

3. The switching regulator as recited in claim 1, wherein the first input switching device is a transistor.

4. The switching regulator as recited in claim 1, wherein the second input switching device is a transistor.

5. The switching regulator as recited in claim 1, wherein the first output switching device is a transistor.

6. The switching regulator as recited in claim 1, wherein the second output switching device is a transistor.

7. The switching regulator as recited in claim 1, wherein the first input switching device is a metal-oxide-semiconductor field-effect transistor (Mos FET).

8. The switching regulator as recited in claim 1, wherein the second input switching device is a Mos FET transistor.

9. The switching regulator as recited in claim 1, wherein the first output switching device is a Mos FET transistor.

10. The switching regulator as recited in claim 1, wherein the second output switching device is a Mos FET transistor.

11. The switching regulator as recited in claim 1, wherein the output load is

a resistor.

12. The switching regulator as recited in claim 2, wherein the low power switching device is a transistor.

13. The switching regulator as recited in claim 2, wherein the low power switching device is a sense FET transistor.

14. The switching regulator as recited in claim 2, wherein the first current mirror, comprises:

a first transistor, having a drain node coupled to the source node of the low power switching device; and

a second transistor coupled to the first transistor, the control node of the first and second transistors coupled to the amplifier, the source node of the second transistor coupled to the source node of the first transistor.

15. The switching regulator as recited in claim 2, wherein the second current mirror, comprises:

a first transistor, having a drain node, a source node, and a control node, the drain node coupled to the control node and the drain node coupled to the first current mirror; and

a second transistor having a drain node, a control node and a source node, the control node coupled to the control node of the first transistor, the source node coupled to the source node of the first transistor, the drain node coupled to the capacitor.