Voltage regulator power management apparatus

• US 6,969,981 B1
• Filed: 09/09/2003
• Issued: 11/29/2005
• Est. Priority Date: 09/09/2003
• Status: Active Grant

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Suzuki, Hidehiko, Fairbanks, John Patrick
• Primary Examiner(s): STERRETT, JEFFREY L
• Application Number:
  US10/658,678
• Time in Patent Office: 812 Days
• Field of Search: 323/265, 323/274, 323/275, 323/281, 323/284, 323/285, 323/299, 323/303
• US Class Current: 323/299
• CPC Class Codes: G05F 1/562 with a threshold detection shunting the control path of the final control device
• CPC Class Codes: H02J 2207/20 Charging or discharging characterised by the power electronics converter
• CPC Class Codes: H02J 7/02 for charging batteries from ac mains by converters
• CPC Class Codes: H02M 1/0032 Control circuits allowing low power mode operation, e.g. in standby mode
• CPC Class Codes: H02M 3/28 using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

Quiescent currents in a circuit that includes a regulator are reduced by disabling selected portions of the circuit. A window comparator is selected activated to evaluate the input voltage such that a first operating mode is activated when the input voltage is within a predetermined voltage range and a second operating mode is activated when the input voltage is outside of the predetermined voltage range. The battery voltage is used a reference signal when the first mode is selected such that a voltage reference circuit can be disabled to reduce power, while the voltage reference circuit is enabled when the second mode is selected. Another comparator circuit is periodically activated to compare the reference signal to the output voltage. The regulator is disabled after the output voltage exceeds a first level. The output voltage collapses below a second level associated, the evaluation and regulation process is repeated.

Claims

1. An apparatus that is arranged to conserve power in a circuit that includes a regulator that provides an output voltage from an input voltage, the apparatus comprising:

a window comparator that is selectively enabled in response to a first control signal, wherein the window comparator is arranged to select a reference mode when enabled, wherein the reference mode corresponds to a first mode when the input voltage is within a predetermined range and a second mode when the input voltage is outside of the predetermined range;

a reference circuit that is selectively enabled in response to a second control signal, wherein the reference circuit is arranged to provide a reference voltage when enabled;

an output comparator that is selectively enabled in response to a third control signal, wherein the output comparator is arranged to selectively activate the regulator by evaluating a reference signal and the output voltage when enabled;

a switching circuit that is arranged to select the reference signal based on the reference mode such that the reference signal is associated with the input voltage in the first mode and the reference signal is associated with the reference voltage in the second mode; and

a power management unit that is arranged to provide the first control signal, the second control signal, and the third control signal such that the reference circuit and the window comparator are enabled to evaluate the input voltage, the reference circuit is disabled when the first mode is selected, and the output comparator is enabled between switching cycles of the regulator.

2. The apparatus of claim 1, wherein the window comparator and the power management unit are further arranged in cooperation such that the window comparator is disabled via the first control signal after the input voltage is evaluated, and wherein the window comparator is re-enabled via the first control signal such that the input voltage is periodically evaluated.

3. The apparatus of claim 1, wherein the window comparator is arranged to monitor at least one of the output voltage and the input voltage such that the output of the window comparator is capable of retriggering switching and calibration cycles in the apparatus.

4. The apparatus of claim 1, wherein the window comparator includes a first comparator circuit that is arranged to assert a first comparison signal when the input voltage is below a first predetermined level, a second comparator circuit that is arranged to assert a second comparison signal when the input voltage is above a second predetermined level, and a logic circuit that is arranged to select the reference mode in response to the first comparison signal and the second comparison signal.

5. The apparatus of claim 4, wherein the first comparator circuit includes a first offset circuit that is arranged to provide the first predetermined level in response to the reference voltage from the reference circuit.

6. The apparatus of claim 4, wherein the second comparator circuit includes a second offset circuit that is arranged to provide the second predetermined level in response to the reference voltage from the reference circuit.

7. The apparatus of claim 4, wherein the first comparator circuit includes a first offset circuit that is arranged to provide the first predetermined level in response to the reference voltage from the reference circuit, and wherein the second comparator circuit includes a second offset circuit that is arranged to provide the second predetermined level in response to the reference voltage from the reference circuit.

8. The apparatus of claim 1, wherein the reference circuit is a band-gap reference circuit.

9. The apparatus of claim 1, further comprising a feedback circuit, wherein the feedback circuit is arranged to provide a scaled version of the output voltage as a feedback voltage to the output comparator such that the output comparator is arranged to compare the feedback voltage to the reference signal.

10. The apparatus of claim 9, wherein the feedback circuit comprises a voltage divider circuit.

11. The apparatus of claim 9, wherein the feedback circuit comprises a voltage divider circuit and another switching circuit, wherein the another switching circuit is arranged to select a tap point from the voltage divider circuit based on a gain adjustment signal.

12. The apparatus of claim 11, further comprising a gain adjustment circuit, wherein the gain adjustment circuit comprises a gain comparator circuit that is arranged to evaluate the input voltage to provide the gain adjustment signal.

13. The apparatus of claim 1, wherein the output comparator includes hysteresis such that positive and negative thresholds associated with the output comparator are different from one another.

14. The apparatus of claim 1, wherein the switching circuit includes a first switch circuit and a second switch circuit, wherein the first switch circuit is arranged to couple the input voltage to the output comparator as the reference signal when the first mode is selected, and wherein the second switch circuit is arranged to couple the reference voltage to the output comparator as the reference signal when the second mode is selected.

15. The apparatus of claim 1, further comprising a voltage scaling circuit that is arranged to provide the reference signal as a scaled percentage of the input voltage when the first mode is selected.

16. An apparatus that is arranged to conserve power in a circuit that includes a regulator that provides an output voltage from an input voltage, the apparatus comprising:

an input comparison means that is arranged to select a reference mode when enabled, wherein the reference mode corresponds to a first mode when the input voltage is within a predetermined range and a second mode when the input voltage is outside of the predetermined range;

a reference voltage means that is arranged to provide a reference voltage when enabled;

an output comparison means that is arranged to selectively activate the regulator by evaluating a reference signal and the output voltage when enabled;

a switching means that is arranged to select the reference signal based on the reference mode such that the reference signal is associated with the input voltage in the first mode and the reference signal is associated with the reference voltage in the second mode; and

a power management means that is arranged to;

enable the input comparison means and the reference voltage means to evaluate the input voltage, disable the reference voltage means when reference mode corresponds to the first mode, and enable the output comparison means between switching cycles of the regulator.

17. An apparatus as in claim 16, further comprising:

a feedback means and a gain adjustment, wherein the feedback means is arranged to provide a sense signal that is related to the output voltage by a selected scaling factor, and wherein the gain adjustment means is arranged to vary the selected scaling factor in response to the input voltage.

18. A method of conserving power in a circuit that includes a regulator, wherein the regulator provides an output voltage from an input voltage, the method comprising:

initiating a quiescent current reduction cycle by;

activating a window comparator and a reference voltage circuit to evaluate the input voltage, wherein the reference voltage circuit is arranged to provide a reference voltage when activated;

selecting a first mode when the input voltage is within a voltage range that is associated with the reference voltage;

selecting a second mode when the input voltage is outside of the voltage range that is associated with the reference voltage;

processing the first mode by;

deactivating the voltage reference;

activating an output comparator;

sensing the output voltage;

enabling the regulator while the sensed output voltage is below a positive threshold that is associated with the output comparator, wherein the positive threshold is related to the input voltage;

disabling the regulator after the desired sensed output voltage is achieved; and

processing the second mode by;

activating the output comparator;

sensing the output voltage;

enabling the regulator while the sensed output voltage is below a positive threshold that is associated with the output comparator, wherein the positive threshold is related to the reference voltage; and

disabling the regulator after the desired sensed output voltage is achieved.

19. The method of claim 18, wherein processing the first mode further comprises:

sensing the output voltage with a feedback circuit that includes a voltage divider.

20. The method of claim 18, wherein processing the first mode further comprises:

monitoring the output voltage with the output comparator after the regulator is disabled, and initiating the quiescent current reduction cycle when the sensed output voltage is below a negative threshold that is associated with the output comparator.

21. The method of claim 18, wherein processing the first mode further comprises:

selecting a gain factor that is associated with the sensed output voltage such that the output voltage is related to the sensed voltage according to the gain factor.

22. The method of claim 18, wherein processing the first mode further comprises:

sensing the input voltage and selecting a gain factor such that the selected gain factor is responsive to the sensed input voltage, wherein the input voltage is related to the sensed voltage according to the gain factor.

23. The method of claim 18, wherein processing the second mode further comprises:

sensing the output voltage with a feedback circuit that includes a voltage divider.

24. The method of claim 18, wherein processing the second mode further comprises:

monitoring the output voltage with the output comparator after the regulator is disabled, and initiating the quiescent current reduction cycle when the sensed output voltage is below a negative threshold that is associated with the output comparator.