Programmable analog bias circuits using floating gate CMOS technology

• US 6,970,037 B2
• Filed: 09/05/2003
• Issued: 11/29/2005
• Est. Priority Date: 09/05/2003
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: ON Semiconductor Corporation
• Inventors: Poenaru, Ilie Marian, Sakhuja, Shashi B.
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): ENGLUND, TERRY LEE
• Application Number:
  US10/656,982
• Publication Number:
  US 20050052223A1
• Time in Patent Office: 816 Days
• Field of Search: 327/434, 327/541, 327/543, 327/566, 327/77, 327/78, 327/89, 365/185.21, 365/185.28, 257/314, 257/315, 257/322
• US Class Current: 327/566
• CPC Class Codes: G05F 3/262 using field-effect transistors only

Abstract

A voltage reference circuit includes storage, programming, and test floating gate transistors. The floating gates of the storage and programming transistors are shorted, while the floating and control gates of the test transistor are shorted. The test and storage transistors are connected between an input terminal and the inputs of a comparator, with the control gate of the test transistor also being connected to the input terminal. A reference voltage is programmed by applying the reference voltage to the input terminal and increasing the net positive charge on the floating gate of the storage transistor (via the programming transistor) until its source voltage matches the source voltage of the test transistor. Then, any test voltage at the input terminal can be compared to the programmed reference voltage by comparing the source voltages of the test and storage transistors.

Claims

1. An integrated circuit (IC) comprising:

a first transistor comprising a first floating gate and a first control gate;

a second transistor comprising a second floating gate and a second control gate, the second floating gate being electrically connected to the first floating gate; and

a third transistor comprising a first gate and a second gate located over the first gate, the first gate being electrically connected to the second gate; and

an input terminal, wherein a drain of the first transistor, a drain of the third transistor and the second gate of the third transistor are each coupled to the input terminal.

2. The IC of claim 1, wherein the first transistor and the third transistor are matched transistors.

3. The IC of claim 2, wherein a physical gate area of the second transistor is substantially larger than a channel area of the second transistor.

4. The IC of claim 1, wherein the second floating gate is formed on an oxide layer, and wherein a portion of the oxide layer is thinned to provide a programming window.

5. The IC of claim 1, further comprising:

a comparator, wherein the first transistor is connected between the input terminal and a first input of the comparator, and wherein the third transistor is connected between the input terminal and a second input of the comparator.

6. The IC of claim 5, wherein the second gate is connected to the input terminal, and

wherein the first control gate is connected to the second control gate.

7. The IC of claim 6, wherein the second transistor further comprises a source and a drain, the source and drain being formed in a substrate,

wherein the IC further comprises a programming control circuit configured to provide a first voltage to the source and the drain of the second transistor and provide a second voltage to the second control gate when a programming signal is asserted, wherein the first voltage and the second voltage are sized to cause charge transfer between the substrate and the second floating gate, and

wherein the programming control circuit is further configured to provide the first voltage to the second control gate and provide the second voltage to the source and drain of the second transistor when a reset signal is asserted.

8. The IC of claim 7, further comprising an output control circuit configured to assert a control signal in response to a comparator output signal from the comparator indicating that an output from the first transistor is greater than an output from the third transistor, wherein the programming control circuit removes the first voltage from the source and the drain of the second transistor when the control signal is asserted.

9. The IC of claim 8, wherein the output control circuit is further configured to provide the comparator output signal as an indicator signal when neither the programming signal nor the reset signal is asserted.

10. A method for creating a reference voltage circuit, the method comprising:

forming a first transistor having a first floating gate and a first control gate;

forming a second transistor having a second floating gate and a second control gate;

electrically connecting the second floating gate to the first floating gate;

forming a third transistor having a first gate and a second gate located over the first gate;

electrically connecting the first gate to the second gate; and

electrically connecting a drain of the first transistor, a drain of the third transistor and the second gate.

11. The method of claim 10, wherein forming the third transistor comprises matching the third transistor to the first transistor.

12. The method of claim 11, wherein forming the second transistor comprises sizing the second floating gate larger than the first floating gate.

13. The method of claim 10, wherein forming the second transistor comprises:

providing an oxide layer;

thinning a first portion of the oxide layer;

forming the second floating gate on the oxide layer.

14. The method of claim 10, wherein the first floating gate, the second floating gate, and the first gate are formed during a first polysilicon process step, and

wherein the first control gate, the second control gate, and the second gate are formed during a second polysilicon process step.

15. A voltage reference circuit comprising:

an input terminal;

a first transistor having a first floating gate;

a second transistor having a first gate and a second gate located over the first gate, the second gate being electrically connected to the input terminal and the first gate; and

a comparator, wherein the first transistor is connected between the input terminal and a first input of the comparator, and wherein the second transistor is connected between the input terminal and a second input of the comparator.

16. The voltage reference circuit of claim 15, wherein the first transistor and the second transistor are matched transistors.

17. The voltage reference circuit of claim 15, further comprising a third transistor having a second floating gate, the second floating gate being electrically connected to the first floating gate.

18. The voltage reference circuit of claim 17, wherein a physical gate area of the third transistor is substantially larger than a channel area of the third transistor.

19. The voltage reference circuit of claim 17, further comprising a programming control circuit configured to program the first transistor by applying a programming voltage to a source and a drain of the third transistor and applying a first offset voltage to a control gate of the third transistor, wherein the source and the drain of the third transistor are formed in a substrate, and wherein the programming voltage and the first offset voltage are sized to cause charge transfer between the substrate and the second floating gate.

20. The voltage reference circuit of claim 19, wherein the programming control circuit is further configured to erase the first transistor by applying an erase voltage to the a control gate of the third transistor and applying a second offset voltage to the source and the drain of the third transistor, the erase voltage and the second offset voltage being sized to cause charge transfer between the second floating gate and the substrate.

21. The voltage reference circuit of claim 15, wherein the first floating gate has a net charge that causes the first transistor to provide a first voltage to the first input terminal of the comparator when a second voltage is applied to a control gate of the first transistor, and

wherein the second transistor provides the first voltage to the second input terminal of the comparator when a reference voltage is applied to the input terminal.

22. A method for comparing a test voltage to a reference voltage, the method comprising:

providing a charge on a floating gate of a first transistor, the charge being sized such that applying a first voltage to a control gate of the first transistor results in a source voltage of the first transistor being equal to a source voltage of a second transistor when the reference voltage is applied to a gate of the second transistor;

applying the first voltage to the control gate of the first transistor;

supplying the test voltage to the floating gate of the second transistor;

supplying the test voltage to a drain of the first transistor and to a drain of the second transistor; and

comparing the source voltage of the first transistor to the source voltage of the second transistor, effectively comparing the test voltage to the reference voltage as represented by the charge provided on the floating gate.

23. The method of claim 22, wherein the first transistor and the second transistor are matched transistors.

24. The method of claim 22, wherein the first voltage is a ground voltage.

25. A method for programming a reference voltage into a storage transistor, the method comprising:

providing a programming potential across a first transistor to generate a net charge on a floating gate of the first transistor;

providing a second transistor, wherein a floating gate of the second transistor is connected to the floating gate of the first transistor;

supplying the reference voltage to a first gate of a third transistor, wherein the first gate of the third transistor is located over, and is electrically connected to a second gate of the third transistor;

supplying the reference voltage to a drain of the second transistor and to a drain of the third transistor; and

removing the programming potential across the first transistor when an output of the second transistor becomes equal to an output of the third transistor, wherein the second transistor functions as the storage transistor which effectively stores the programmed reference voltage.

26. The method of claim 25, wherein the second transistor and the third transistor are matched transistors.

27. A method for comparing a test voltage to a reference voltage, the method comprising:

providing a first transistor having a first terminal coupled to a test voltage input terminal, a second terminal, a floating gate, and a control gate,

providing a second transistor having a first terminal coupled to the test voltage input terminal, a second terminal, a first gate, and a second gate located over the first gate, wherein the first gate of the second transistor is electrically connected to the second gate of the second transistor;

providing a charge on the floating gate of the first transistor, the charge being sized such that when a first voltage is applied to the control gate of the first transistor, an output at the second terminal of the first transistor is equal to an output at the second terminal of the second transistor when the reference voltage is applied to the second gate of the second transistor;

applying the first voltage to the control gate of the first transistor;

supplying the test voltage via the test voltage input terminal; and

comparing the output at the second terminal of the first transistor to the output at the second terminal of the second transistor, effectively comparing the test voltage to the reference voltage as represented by the charge provided on the floating gate.

28. The method of claim 27, wherein the first transistor and the second transistor are matched transistors.

29. The method of claim 27, wherein the first voltage is a ground voltage.

30. The method of claim 27, further comprising:

placing an output signal in a first state when the output at the second terminal of the first transistor is greater than the output at the second terminal of the second transistor, wherein the first state indicates that the reference voltage is greater than the test voltage; and

placing the output signal in a second state when the output at the second terminal of the first transistor is less than the output at the second terminal of the second transistor, wherein the second state indicates that the reference voltage is less than the test voltage.